Keynote Speeches

Professor Jie Wu, Ph.D. (Florida Atlantic) Jie Wu received the B.S. and M.S. degrees from Shanghai University of Science and Technology (now Shanghai University) in 1982 and 1985, respectively; the Ph.D. degree from Florida Atlantic University. He is now a Professor at Department of Computer Science and Engineering, Florida Atlantic University. He has published over 200 papers in various journals and conference proceedings. His research interests are in the areas of wireless networks and mobile computing, routing protocols, fault-tolerant computing, and interconnection networks. He served on many conference organization committees. Dr. Wu is on the editorial board of IEEE Transactions on Parallel and Distributed Systems and was a co-guest-editor of IEEE Computer and Journal of Parallel and Distributed Computing. He is the author of the text "Distributed System Design" published by the CRC press. He was also the recipient of the 1996-97 and 2001-2002 Researcher of the Year Award at Florida Atlantic University. Dr. Wu has served as an IEEE Computer Society Distinguished Visitor. He is a Member of ACM and a Senior Member of IEEE. More ...

Title: "Localized Algorithms and Their Applications in Ad Hoc Wireless Networks"

Abstract: An ad hoc wireless network is a special type of wireless multi-hop network without infrastructure or centralized administration. As a result of the mobility of their nodes, ad hoc wireless networks are characterized by dynamically changing topologies. A localized algorithm is a special distributed algorithm where each node performs an exceedingly simple task based on local information, with no information sequentially propagated globally in the network. The importance of localized algorithms is their scalability in mobile environments. Decisions made based on localized algorithms are adjustable to the change (such as a topological one) due to the mobile node. We discuss a generic framework that can capture many existing localized broadcast algorithms in ad hoc wireless networks. The framework can easily integrate other objectives such as energy-efficient design and reliability that ensures broadcast coverage. In addition, the framework is extensible to cover other collective communication, which includes one-to-many (multicasting), all-to-one (reduction or aggregation), and all-to-all (gossiping).

Satoshi SEKIGUCHI, Director, Grid Technology Research Center, National Institute of Advanced Industrial Science and Technology, Japan He was born in 1959, received B.S. from Department of Information Science, Faculty of Science, the University of Tokyo in 1982, and M. SE. from University of Tsukuba in 1984 respectively. He joined Electrotechnical Laboratory, Agency of Industrial Science and Technology in 1984 to engage research in high performance and parallel computing widely from the computer architecture, compiler, numerical algorithm, performance evaluation as well as its applications. He served as the deputy director of Research Institute of Information Technology, AIST in 2001, and is currently the founding director of Grid Technology Research Center (GTRC), AIST since 2002. He is a member of IEEE, SIAM, IPSJ. He is also serving as one of the steering committee members of the Global Grid Forum (GGF). Since the dawn of grid era, definitely he has been one of technology and community leaders, who is in particular one of the PIs of the Ninf project since 1996 being developed as a reference implementation of current GridRPC GGF standard draft, the founder of the Asia Pacific Grid partnership (ApGrid), and chairing Japan Grid Consortium (JpGrid).  . More ...

Title: "Grid Project status overview in Japan"

Abstract: The grid is an emerging paradigm for organizing scientific work, and for sharing resources, such as computers, networks, storage capacity, or large-scale scientific instruments, but also data, and eventually knowledge. The presentation will give an introduction to activities of recently initiated Japanese grid projects, including such as Business Grid, National Research Grid Initiative, Asia Pacific Grid and several AIST activities. Last year, following discussion at the Council for Science and Technology Policy in the Cabinet Office in Japan, two proposals for large grid projects to start during the this fiscal year were recommended for funding. One of them, termed "Research Grid", aims at the deployment of a new grid enabled infrastructure for scientific research. This is a grid "grand challenge" project, yet is an extension to the classical concept of the grid. The other one, termed "Business Grid", has objectives that go far beyond the classical concept of the grid and towards exploring the use of grid infrastructures in a business environment. New business models that can be put on top of the grid are a major concern of this endeavor, as are such issues as security and reliability. By opening the door towards the business field, OGSA has provided for an important stimulus towards launching this endeavor. As you all know, the grid is no longer owned by engineers and researchers alone, but is now attempting to venture in the business world. Finally, looking around countries in the Asian Pacific region, we realize a considerable number of quite significant grid projects that have been proposed as well as an increasing number of projects that actually got funded. It is the right time to make further steps and advance the grid further toward more practical platform for everyone, a vision that I believe we all share. We have continued the discussion with grid technology leaders across the Asia Pacific region, in order to explore possible directions for promoting grid technology on the ApGrid. Today, the goal of the ApGrid remains with providing a full-scale grid environment to enable practical experiment with grids and grid technologies. The status and recent experimental results will be covered.

Professor Francis Lau, BSc(Acadia); MMath, PhD(Waterloo) Francis Lau is the Head of Department of Computer Science & Information Systems at The University of Hong Kong. He received his PhD in computer science from the University of Waterloo, Canada in 1986. He is active in the research field and community of parallel and distributed computing. His main research interests are in the fundamental issues of load balancing and process migration in parallel systems. He is a Golden Core member of the IEEE Computer Society and received an IEEE Third Millennium Medal in 2000 for outstanding achievements and contributions to the Society. He is on the editorial boards of the Journal of Interconnection Networks (JOIN) and the International Journal of High Performance Computing and Networking (IJHPCN). More ...

Title: "Towards a Single System Image for High-Performance Java"

Abstract: Multithreaded programming in Java is an attraction to programmers writing high-performance code if their programs can exploit the multiplicity of resources in a cluster environment. Unfortunately, the common platforms today have not made it possible to allow a single Java program to span multiple computing nodes, let alone dynamically to cling on to additional nodes or migrate some of its executing code from one node to another for load balancing reasons during runtime. As a result, programmers resort to parallel Java programming using such devices as MPI. Ideally, a "single system image" (SSI) offered by the cluster is all that is needed. But the purist's idea of SSI is not at all easy to achieve if indeed it can be achieved. A workable SSI solution will likely require a major concerted effort by designers on all fronts, from those of the hardware and OS to those looking after the upper or middleware layers. In the meantime, partial SSI implementations offer limited but useful capabilities and help clear the way for more complete SSI implementations in the future. We present in this talk our brave attempts to provide partial SSI in a cluster for the concurrent Java programmers, and discuss how the design of the Java Virtual Machine has made it possible (or has given us some of the troubles). At the core of our present design are a thread migration mechanism that works for Java threads compiled in just-in-time mode, and an efficient global object space that enables cross-machine access of Java objects. We close Multithreaded programming in Java is an attraction to programmers writing high-performance code if their programs can exploit the multiplicity of resources in a cluster environment. Unfortunately, the common platforms today have not made it possible to allow a single Java program to span multiple computing nodes, let alone dynamically to cling on to additional nodes or migrate some of its executing code from one node to another for load balancing reasons during runtime. As a result, programmers resort to parallel Java programming using such devices as MPI. Ideally, a "single system image" (SSI) offered by the cluster is all that is needed. But the purist's idea of SSI is not at all easy to achieve if indeed it can be achieved. A workable SSI solution will likely require a major concerted effort by designers on all fronts, from those of the hardware and OS to those looking after the upper or middleware layers. In the meantime, partial SSI implementations offer limited but useful capabilities and help clear the way for more complete SSI implementations in the future. We present in this talk our brave attempts to provide partial SSI in a cluster for the concurrent Java programmers, and discuss how the design of the Java Virtual Machine has made it possible (or has given us some of the troubles). At the core of our present design are a thread migration mechanism that works for Java threads compiled in just-in-time mode, and an efficient global object space that enables cross-machine access of Java objects. We close with some thoughts on what can be done next to popularize our or similar approaches.

Dr. Ken'ichi Itakura, BE, ME, PhD (Tsukuba) He received his B.E. and M.E. degrees in information engineering from University of Tsukuba in 1993 and 1995, respectively. He received his Ph.D. degree in information science, also from the University of Tsukuba, in 1999. He worked at the Center for Computational Physics, University of Tsukuba by a Research Associate in 1999 and 2000. He was also engaged in the research and development of the Earth Simulator. He is now engaged at the Earth Simulator Center. He is a member of the IEEE Computer Society and the Information Processing Society of Japan. More ...

Title: "The Earth Simulator"

Abstract: The Earth Simulator is a high speed parallel computer developed for research on global environment change. Target sustained performance of the Earth Simulator is set to 1,000 times higher than that of the most frequently used supercomputers around 1996 in the climate research field. The Earth Simulator is the fastest supercomputer in the world today. An attempt to understand large scale phenomena on the earth such as global warming and EL Ni˜no events by numerical simulations is very important and challenging. The Earth Simulator project has been started by the Science and Technology Agency of Japan (STA) in 1997 aiming to understand and predict global environment change of the earth.
The Earth Simulator Research and Development Center (ESRDC) was a joint team established by National Space Development Agency of Japan (NASDA), Japan Atomic Energy Research Institute (JAERI) and Japan Marine Science and Technology Center (JAMSTEC). ESRDC engaged in the development of the Earth Simulator that is the main resource for the project. The Earth Simulator contributes not only to the promotion of research on global environment change, but also to the promotion of computational science and engineering. Between July 2002 and March 2003, there were only five whole system failures. Twice were problems of Interconnection Network Nodes and three times were troubles with job scheduling operation software. The Earth Simulator consists of 640 processor nodes and it has an enormous number of parts; 5120 vector processors, 1 million memory chips, 20,000 memory controller chips, 160,000 serial-parallel translate chips and so on. The storage system consists of RAID5 disk arrays which helps to save user data from disk troubles. Some small errors are happen every day. However, practically every error is recovered by using correcting system or retrying by hardware and software. We check the diagnosis reports and do preventive maintenance on nodes in which some recoverable errors were happened. Now, one of the most important problems is how to store and move massive amount of user data. This problem has two sides. One is how to provide processing nodes with data from permanent storage systems. Another is how to retrieve data from the Earth Simulator. The Earth Simulator has such high performance that the product data becomes enormous size. We have a tape cartridge system which provides peta byte class storage. However, the accessibility of the tape system is not so convenient which creates problems form users and wastes system resources. We plan to replace this with a hierarchy storage system, consisting of disks and tapes.

Professor Yi Pan, BS, ME (Tsinghua), PhD (Univ Pittsburgh) Dr Pan is currently with the Department of Computer Science at Georgia State University. His research interests include parallel and distributed computing, optical networks and wireless networks. He has co-edited 9 books/proceedings, and published more than 130 research papers including over 60 journal papers. He received many awards from agencies such as NSF, AFOSR, JSPS, IISF and Mellon Foundation. Dr. Pan has served as an editor-in-chief or editorial board member for 8 journals including 3 IEEE Transactions and guest editor for 7 special issues. He has organized several international conferences and workshops and has also served as a TPC member for several major international conferences such as INFOCOM, GLOBECOM, ICC, IPDPS, and ICPP. His research results have been cited by more than 100 researchers worldwide. More ...

Title: "Computing on the Restricted LARPBS Model"

Abstract: Many algorithms have been designed on models using pipelined optical buses by several research groups. Linear array with a reconfigurable pipelined bus system (LARPBS) is one such model. The results in the literature show that most of the basic operations can be executed in O(1) bus cycles on the LARPBS model. However, since a bus cycle time is proportional to the number of processors attached to it, a bus cycle is not really a constant time when the number of processors is large. In this paper, a more realistic model called restricted-LARPBS (RLARPBS) model is proposed, where a bus cycle can only accommodate a limited number of messages. We use a parameter to characterize this feature. Under the new model, we propose several basic data movement operations. Their time complexities are also analyzed.