AY 2017 Undergraduate School Course Catalog AY 2017 Undergraduate School Course Catalog AY 2017 Undergraduate School Course Catalog
| 2018/01/30 |
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| 開講学期 ／Semester |
2017年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
Toshiaki Miyazaki |
| 担当教員名 ／Instructor |
Junji Kitamichi, Toshiaki Miyazaki |
| 推奨トラック ／Recommended track |
SD |
| 履修規程上の先修条件 ／Prerequisites |
F5 |
| 更新日／Last updated on | 2017/03/02 |
|---|---|
| 授業の概要 ／Course outline |
[NOTE] This course is subject to be cancelled at the end of AY2017. The students will not be able to re-take this course in AY2018 if they fail AY2017. Microprocessors (MPU) are popular today, and they are used, in not only ordinary PCs and workstations but also many consumer and industry products. In this course, base on the basic knowledge of MPUs learned in “Computer Architecture” course, students will learn advanced knowledge and skill including high-performance and low-power technologies introduced in modern MPUs. In addition, the students will learn how to control peripheral circuits with an MPU through some exercises. In the exercises, each student should realize an MPU-based system in an evaluation board mounted on an FPGA (Field Programmable Gate Array: an LSI in which logic circuits can be freely changed by the user). More precisely, after realizing an MPU with peripheral control circuits, the students will develop some programs using an assembly language to control peripherals. Through the abovementioned exercises, the student can understand the concept of interrupts and how to control peripherals with interrupt signals. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
- To learn the inside of MPUs, which students learned in “Computer Architecture” course. - To understand overviews of high-speed and low-power technologies introduced in modern MPUs. - To learn how to control peripherals with interrupt signals by developing control programs using an assembly language. - To lean a basic design flow for hardware using an FPGA. |
| 授業スケジュール ／Class schedule |
- Introduction - Overview of a 16-bit RISC for education - Sub-routines and I/O interrupts (2 periods) - Peripheral interface - Logic circuits and logic synthesis - FPGA technologies - Reconsideration of computer architecture (I) (2 periods) - Reconsideration of computer architecture (II) (2 periods) - Advanced technologies (I) : Performance improvement - Advanced technologies (II) : Customization, low-power - Embedded MPUs - Multi-processors and related technologies |
| 教科書 ／Textbook(s) |
Original handouts will be distributed via the course WEB site. The detail information will be announced in the first lecture. |
| 成績評価の方法・基準 ／Grading method/criteria |
Examination(50%), Exercise report(50%). (No makeup examination) [NOTE] Lecture points are mainly the result of the final examination. However, if the final score is not sufficient, attendance and the results of short tests requested at the end of each lecture will be considered. The exercise points will be evaluated by attendance and reports. |
| 履修上の留意点 ／Note for course registration |
[NOTE] This course is subject to be cancelled at the end of AY2017. The students will not be able to re-take this course in AY2018 if they fail AY2017. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Prerequisites - Computer Architecture Related courses - Logic Circuit Design - Advanced Logic Circuits - Operating System Course website It will be announced at the first lecture References "コンピュータの構成と設計 第5版 (上）" Patterson and Hennessy Publisher: 日経BP社, ISBN: 4822298426 上巻 "コンピュータの構成と設計 第5版 (下）" Patterson and Hennessy Publisher: 日経BP社, ISBN: 4822298434 下巻 "HDLによるVLSI設計―VerilogHDLとVHDLによるCPU設計 第２版" 深山正幸 他著 Publisher: 共立出版, ISBN: 4320120272 Reference for Exercise "作りながら学ぶコンピュータアーキテクチャ" 小栗清【監修】 天野英晴 西村克信【共著】 Publisher: 培風館, ISBN: 4563014117 |
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| 開講学期 ／Semester |
2017年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
Tsuneo Tsukahara |
| 担当教員名 ／Instructor |
Maxim V. Ryzhii, Tsuneo Tsukahara |
| 推奨トラック ／Recommended track |
VD |
| 履修規程上の先修条件 ／Prerequisites |
NS4 |
| 更新日／Last updated on | 2017/01/13 |
|---|---|
| 授業の概要 ／Course outline |
This beginning course in electronic circuits covers resistance, current, Ohm’s Law, Kirchhoff’s laws, and circuit parameters. Other topics covered in this course include magnetism and electromagnetic induction, inductance, capacitance, and the introduction of periodic functions. Because the CSE laboratories in the 2nd grade covered basic electrical circuits so far, this course provides in-depth theoretical backgrounds. Moreover, as the fundamentals of electronic circuits, this course will cover semiconductor devices and basic circuits. A hands-on approach is emphasized through laboratory exercises in which the student develops skills using the basic test equipment. Starting from series LC resonant circuits, parallel LC resonant circuits will be covered. Moreover, we will cover sinusoidal-wave extraction from pulse waves using the LC resonant circuits. This experiment is based on the Fourier-series expansions of signals. Finally, MOSFET amplifiers with resistive loads will be covered. The student can also learn close relationship between analog amplifiers and digital inverters observing pulse responses of the MOSFET amplifier. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
The primary goals of this course are: 1. To introduce the student to electrical and scientific numbers as applied to the analysis of electrical and electronic circuits; 2. To familiarize the student with the basic properties and quantities associated with electricity; 3. To familiarize the student with the basic laws and theorems used in the analysis of electrical and electronic circuits and in the computation of circuit values; 4. To develop the student’s ability to analyze, construct and test electric and electronic circuits connected in various configurations Students will be able to: 1. Convert ordinary numbers to power-of-ten expressions. 2. Express any number in correct scientific notation form. 3. Express electrical quantities with appropriate engineering prefixes. 4. Study, analyze, construct, and test electric circuits with components connected in series, in parallel, and in series-parallel. 5. Compute total resistance, total current in series, in parallel, and in series-parallel circuit as well as compute voltage drops and power dissipation. 6. Identify capacitors and inductors and analyze capacitive and inductive circuits using complex numbers. 7. Measure circuit values using electronic test equipment. 8. Analyze, construct, and test RLC electric circuits and basic electronic circuits. |
| 授業スケジュール ／Class schedule |
Lecture and Experiment classes will be independently provided on different weeks. Lectures: 7 weeks 1. Components, Quantities and Units. 2. Voltage, Current, Resistance. 3. Circuit elements. 4. Ohm’s Law and Kirchhoff’s Laws. 5. Series and parallel circuits 6. Circuit analysis: node-method, mesh-method, Thevenin and Norton equivalents and superposition theorem. 7. Capacitance and Inductance, Response of RL, RC, and RLC circuits. 8. Sinusoidal steady state power calculations 9. Transformer circuits. 10. Series and parallel resonance. 11. Basic semiconductor devices and circuits 12. Impedance matching. 13. MOSFET operation and application Experiments: 8 weeks Topic 1: A review of LC-resonant circuits and in-depth experiments: the behavior of inductor and capacitor voltages at the resonance and analysis of parasitic series resistors. Topic 2: Sinusoidal-wave extraction from pulse waves using LC resonant circuits: Verifying the Fourier series. Topic 3: Review of MOSFET operations and related exercises. Topic 4: Measuring MOSFET I-V curves and DC-transfer-function curves of an MOSFET amplifier using a resistive load (1). Topic 5: Measuring MOSFET I-V curves and DC-transfer-function curves of an MOSFET amplifier using a resistive load (2). Topic 6: Measuring gains and AC-transfer-function curves of an MOSFET amplifier using a resistive load. Topic 7: Measuring gains and AC-transfer-function curves of a CMOSFET amplifier: Understanding close relationship between analog amplifiers and digital inverters. Topic 8: Supplemental experiments (e.g. Common-gate MOSFET amplifier) |
| 教科書 ／Textbook(s) |
Especially, this is used in Experiment classes. M. Ikeda, "Introduction to MOS Electronic Circuits", ISBN: 978-4-901683-77-7 （池田 誠、「MOSによる電子回路基礎」 ISBN：978-4-901683-77-7） |
| 成績評価の方法・基準 ／Grading method/criteria |
Lecture: Terminal Exam (50%) Experiment: Reports (50%) |
| 履修上の留意点 ／Note for course registration |
Course Prerequisites: Semiconductor Devices, Fourier Analysis Formal prerequisites:NS4 Semiconductor Devices |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
1. Schaum's Outline of Electric Circuits, ISBN: 0071393072 2. Sato, “Basics of Electric Circuits”, ISBN: 978-4-274-20901-7 （佐藤、「電気回路基礎」ISBN: 978-4-274-20901-7） |
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| 開講学期 ／Semester |
2017年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
Yasuhiro Hisada |
| 担当教員名 ／Instructor |
Yasuhiro Hisada |
| 推奨トラック ／Recommended track |
VD |
| 履修規程上の先修条件 ／Prerequisites |
S2 |
| 更新日／Last updated on | 2017/03/02 |
|---|---|
| 授業の概要 ／Course outline |
[NOTE] This course is subject to be cancelled at the end of AY2017. The students will not be able to re-take this course in AY2018 if they fail AY2017. the various analogue circuits using semiconductor devices is learned. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
The fundamentals of transistor and the characteristic of amplifier are learned. The behavior and characteristic of various circuits using Operational Amplifier are also learned. It is necessary to understand the relations between circuit equation and real circuits. |
| 授業スケジュール ／Class schedule |
1. Static charactaristic of bipolar transistor 2. T-type equivalent circuit of the bipolar transistor 3. h-type equivalent circuit 4. The bias circuit of the bipolar transistor 5. Charactaristic of amplifire using bipolar transistor 6. Characteristic of FET 7. Midterm examination 8. A negative feedback circuit 9. Introduction of operational amplifier 10. Applied circuit of the op-amp 11. Differential amplification circuit 12. Oscillation circuit 13. Analog-Digital interface circuits #1 14. Analog-Digital interface circuits #2 15. Analog-Digital interface circuits #3 |
| 教科書 ／Textbook(s) |
石橋幸男 著 「電子・情報工学講座４ アナログ電子回路」 培風館 １９９３年９月 Other materials will be provided, as needed. |
| 成績評価の方法・基準 ／Grading method/criteria |
Mid-term Exam. (40%), Final Exam. (40%), Quiz (20%) |
| 履修上の留意点 ／Note for course registration |
[NOTE] This course is subject to be cancelled at the end of AY2017. The students will not be able to re-take this course in AY2018 if they fail AY2017. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
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| 開講学期 ／Semester |
2017年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
4th year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
Junji Kitamichi |
| 担当教員名 ／Instructor |
Junji Kitamichi, Yuichi Okuyama, Abderazek Ben Abdallah |
| 推奨トラック ／Recommended track |
SD |
| 履修規程上の先修条件 ／Prerequisites |
F5 & F6 |
| 更新日／Last updated on | 2017/01/25 |
|---|---|
| 授業の概要 ／Course outline |
This course provides students with experience in embedded systems design. The course introduces issues in upstream design in embedded system and RTOS for real time systems. There are also weekly laboratory sessions on design of a microprocessor-based embedded system including one or more custom peripherals. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
To serve as a capstone design course to tie together the computer engineering curriculum via the design of a complete embedded system involving multiple communicating components. |
| 授業スケジュール ／Class schedule |
1. Introduction 2. System Architecture 3. Upstream Design in Embedded System 4. System Modeling(State Machine) 5. System Modeling(UML) 6. Object Oriented 7. Multi-task System 8. Multi-task Programming 9. Real Time OS - Toppers 10. Real Time OS - Time Constraints 11. Real Time OS - Other Functions 12. Real Time OS - Priority Inversion 13. Real Time Scheduling 14. Analysis of Schedulability 15. Software Tests The order of some items would be changed. |
| 教科書 ／Textbook(s) |
Text(s)Materials will be provided by instructor. Materials are based on following book and etc. 組み込みシステム開発に役立つ理論と手法 Author: 藤倉 俊幸(Toshiyuki Fujikura) Edition: 2012 Publisher:CQ出版社 ISBN-10: 0123743974, ISBN-13: 978-0123743978 |
| 成績評価の方法・基準 ／Grading method/criteria |
Final examination (50%), and reports of exercises (50%). |
| 履修上の留意点 ／Note for course registration |
F5 Computer Architecture F6 Operating Systems |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Course website and other reference material will be given by the instructor during the first class. |
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| 開講学期 ／Semester |
2017年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
4th year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
Naohito Nakasato |
| 担当教員名 ／Instructor |
Naohito Nakasato, Stanislav G. Sedukhin |
| 推奨トラック ／Recommended track |
SD |
| 履修規程上の先修条件 ／Prerequisites |
F5 |
| 更新日／Last updated on | 2017/01/30 |
|---|---|
| 授業の概要 ／Course outline |
A large change in the computing world has started in the last few years: not only are the fastest computers parallel, but nearly all computers will soon be parallel, because the physics of semiconductor manufacturing will no longer let conventional sequential processors get faster year after year, as they have for so long (roughly doubling in speed every 18 months for many years). So all programs that need to run faster will have to become parallel programs. As multi-core processors and cluster systems have become ubiquitous, he demand for parallelization methods and technologies is also increasing.> Parallel computer architecture is a field related to the development of these methods and computing technologies. Parallelism can be applied to different levels of a computer system and different challenges and solutions exist. . |
| 授業の目的と到達目標 ／Objectives and attainment goals |
The objective of this course is to understand the basic knowledge for designing and evaluating parallel computer architectures. The class will focus on understanding the elements that characterize parallel architectures, technical challenges, and possible solutions. Exercises in parallel programming with the Open MP and Message Passing Interface MPI) will provide an understanding of parallel architectures through actual programming. |
| 授業スケジュール ／Class schedule |
1 Introduction to Parallel Computing 2 Basics on Parallel Computing 3 On Floating-point Arithmetic 4 Single Process Performance Tuning(1) 5 Single Process Performance Tuning(2) 6 Shared Memory Computers(1) 7 Shared Memory Computers(2) 8 Parallel Algorithm/Architecture Co-Design. 9 Multi-core and Many-core Processors 10 Graphic Processing Units(1) 11 Graphic Processing Units(2) 12 Distributed Memory Machines and Programming(1) 13 Distributed Memory Machines and Programming(2) 14 Future Trends in High Performance Computing 15 Student Presentation and Discussion |
| 教科書 ／Textbook(s) |
Text(s)Materials will be provided by instructor. |
| 成績評価の方法・基準 ／Grading method/criteria |
Exercises 70% Final examination/presentation 30% |
| 履修上の留意点 ／Note for course registration |
F5 Computer Architecture |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Course Website in 2016: http://galaxy.u-aizu.ac.jp/note/wiki/PCA2016 |
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| 開講学期 ／Semester |
2017年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
Yukihide Kohira |
| 担当教員名 ／Instructor |
Yukihide Kohira |
| 推奨トラック ／Recommended track |
SD,VD |
| 履修規程上の先修条件 ／Prerequisites |
NS4 & L5 |
| 更新日／Last updated on | 2017/01/30 |
|---|---|
| 授業の概要 ／Course outline |
Due to the progress of the LSI technology, developing electronics and advancing performance are achieved. Although the speed of a transistor is improved by the progress of the process technology in LSI, it increases the routing delay. Since the routing delay is determined by the layout process, it is important to understand the knowledge about layout design. In this class, students learn the knowledge of the LSI design. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
1. Students will be able to understand the knowledge of the LSI design. 2. Students will be able to understand how to determine the LSI circuit performance and the power consumption. 3. Students will be able to understand how to design, evaluate, and verify LSI circuits by applying LSI design flow from logic synthesis to layout design in CAD tools. |
| 授業スケジュール ／Class schedule |
Lecture 1. Introduction 2. Review of semiconductor devices 3. Review extermination 4. LSI design flow, memory 5. LSI layout design 6. Performance of CMOS circuits 7. Midterm examination 8. Power consumption of CMOS circuits 9. Placement and routing algorithm, timing verification 10. Scaling 11. Summary Exercise 1-3. CMOS circuit design in transistor level 4-6. Layout design for CMOS circuits (Full custom design) 7-8. Performance of CMOS circuits 9. Power consumption of CMOS circuits 10-13. Layout design for CMOS circuits (Design automation) # The slots for lectures and exercises are changed in the progress of lectures. |
| 教科書 ／Textbook(s) |
牧野 博之，益子 洋治，山本 秀和「半導体LSI技術」共立出版 |
| 成績評価の方法・基準 ／Grading method/criteria |
The plan of evaluation is as follows: Review examination: 10% Midterm examination: 30% Final examination: 30% Exercises: 30% Additionally, the behavior in classes is also evaluated. |
| 履修上の留意点 ／Note for course registration |
Students are required to have the knowledge of the following courses: L5 CSE laboratories, NS4 Semiconductor Devices, F4 Logic Circuit Design and S7 Advanced Logic Circuit Design. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Reference 國枝 博昭「集積回路設計入門」コロナ社 |
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| 開講学期 ／Semester |
2017年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
Hiroshi Saito |
| 担当教員名 ／Instructor |
Hiroshi Saito, Yoichi Tomioka |
| 推奨トラック ／Recommended track |
SD,VD |
| 履修規程上の先修条件 ／Prerequisites |
F4 |
| 更新日／Last updated on | 2017/03/08 |
|---|---|
| 授業の概要 ／Course outline |
Currently, the most of digital integrated circuits is designed by using a Hardware Description Language (HDL) and electronic design automation (EDA) tools. Therefore, it is very important to know how to model functionalities using an HDL and how EDA tools synthesize digital integrated circuits. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
The main purpose of this course is to study a realistic logic design using an HDL and a logic synthesis tool. In exercises, students specify functionalities implemented in VLSIs using an HDL and synthesize logic circuits using a logic synthesis tool. In addition, students evaluate implemented circuit on an evaluation board which has a reconfigurable device called Field Programmable Gate Array (FPGA). |
| 授業スケジュール ／Class schedule |
Lectures Week 1 Electronic Design Automation Week 2 Review of logic circuit design Week 3 Verilog Hardware Description Language (Verilog HDL) Week 4 Modeling of circuits using Verilog HDL Week 5 Overview of logic synthesis tools Week 6 Case study: Altera Quartus Prime Week 7 Two-level logic minimization Week 8 Multi-level logic optimization Week 9 Technology mapping Week 10 Logic synthesis for FPGAs Week 11 Sequential circuit synthesis Week 12 Power optimization and design for testability Week 13 Logic verification, Static timing analysis, and power analysis Week 14 Summary Week 15 Other topics Exercises Week 1 How to use Altera Quartus Prime? Week 2 How to use ModelSim-Altera? Week 3 How to use TimeQuest Timing Analyzer and PowerPlay Power Analyzer? Week 4 Modeling of circuits using Verilog HDL Week 5 and 6 Modeling and synthesis of combinational circuits Week 7 Modeling and synthesis of memory logics Week 8-11 Modeling and synthesis of a counter and implementation on an FPGA Week 12-15 Modeling and synthesis of a processor |
| 教科書 ／Textbook(s) |
Not assgined |
| 成績評価の方法・基準 ／Grading method/criteria |
Reports (45%) and final examination (55%) No re-examination |
| 履修上の留意点 ／Note for course registration |
Formal prerequisites:F4 Logic Circuit Design Related courses: Computer Architecture, VLSI Design, Embedded System |
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| 開講学期 ／Semester |
2017年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
4th year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Abderazek Ben Abdallah |
| 担当教員名 ／Instructor |
Abderazek Ben Abdallah |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/03/02 |
|---|---|
| 授業の概要 ／Course outline |
[NOTE] This course is subject to be cancelled at the end of AY2017. The students will not be able to re-take this course in AY2018 if they fail AY2017. This course covers topics on the engineering of computer software and hardware systems. Students will acquire the knowledge base and hands-on skills needed to build well-engineered computer systems. The main topics covered are: impact of technology and software on ISA, clocking issues, cache organization, memory management, virtual memory, scheduling, branch prediction, and reliability and performance evaluation. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
- Specify computer system engineering requirements - Learn important hardware/software optimization techniques for microprocessors - Evaluate trade-offs in computer system design |
| 授業スケジュール ／Class schedule |
1. Introduction 2. Influence of Technology and Software on Instruction Sets 3. Hardwired, Non-pipelined ISA Implementation 4. Advanced Instruction Pipelining and Hazards 5. Hazards and Clocking Issues I 6. Hazards and Clocking Issues II 7. Memory Hierarchy 8. Cache Organization 9. Exceptional Control Flow I 10.Exceptional Control Flow II 11.Virtual Memory 12. Dynamic Memory Allocation 13. Multicore System Architecture 14. Summary |
| 教科書 ／Textbook(s) |
Book Title: Computer Systems: A Programmer's Perspective (CS:APP), 2nd Edition, by Randal E. Bryant and David R. O'Hallaron Prentice Hall, 2003, ISBN 0-13-034074-X |
| 成績評価の方法・基準 ／Grading method/criteria |
Final examination (60%), and reports of exercises (40%). |
| 履修上の留意点 ／Note for course registration |
- Computer Organization and Design - Computer Architecture Formal prerequisites:None [NOTE] This course is subject to be cancelled at the end of AY2017. The students will not be able to re-take this course in AY2018 if they fail AY2017. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Course web page and reference materials will be given during the first lecture. |