AY 2017 Graduate School Course Catalog AY 2017 Graduate School Course Catalog AY 2017 Graduate School Course Catalog
| 2018/01/30 |
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| 開講学期 ／Semester |
2017年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Tsuneo Tsukahara |
| 担当教員名 ／Instructor |
Tsuneo Tsukahara, Yukihide Kohira |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/13 |
|---|---|
| 授業の概要 ／Course outline |
Because CMOS technologies are widely used in modern electronics, we need advanced knowledge of scaled CMOS devices. Moreover, recently the demand for mixed-signal LSIs, including analog and RF (Radio Frequency) circuits, is very rapidly increasing, especially for consumer electronics and communication equipments. This course covers theoretical and practical aspects of CMOS devices and modeling. First, fundamentals of semiconductor devices, which are undergraduate level, will be reviewed and distributed-constant circuit models will be also provided. Then, in-depth modeling of MOS transistors will be introduced using the textbook (Chapters 2 to 5). This helps you design VLSIs using the deep sub-micron CMOS in the near future. Finally, design examples of mixed-signal LSIs will be overviewed. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
At the end of the course the student should be able to: ・Explain the basic concepts of the semiconductor devices. ・Design CMOS VLSI chips. ・Understand MOS transistor models used for design of mixed-signal LSIs ・Forecast the future direction of VLSI technologies. |
| 授業スケジュール ／Class schedule |
1. Reviewing fundamentals of semiconductor devices (undergraduate level) 2. Distributed-constant circuit models and thermal noise basics 3. Basic Device Physics (Chapter 2): MOS capacitors, High-field effects 4. MOSFET Devices (Chapter 3) 5. CMOS Device Design (Chapter 4): Scaling, Variations of threshold voltage 6. CMOS Performance Factors [1] (Chapter 5): Basic circuits, Parasitic elements 7. CMOS Performance Factors [2] (Chapter 5): Sensitivity of delay to device parameters, Advanced CMOS Devices 8. Examples of mixed-signal LSIs: CMOS RF circuits etc. |
| 教科書 ／Textbook(s) |
1. Y. Taur and T. H. Ning, "Fundamentals of Modern VLSI Devices", Cambridge University Press, ISBN 0-521-55959-6 (paperback), (1998). |
| 成績評価の方法・基準 ／Grading method/criteria |
1. At the end of the course, topics are given to students. They are required to survey and study about the topics by themselves. |
| 履修上の留意点 ／Note for course registration |
Under Graduate Courses: ・Electronic Circuits ・Semiconductor Devices ・VLSI Design ・VLSI Device Technology Also ・"Logic Circuit Design" and "Advanced Logic Circuit Design" courses are related. Graduate School Courses: VLSI Design related courses are relevant to this course. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
1. T. Tsividis, “Operation and Modeling of the MOS Transistors,” 2nd Edition, ISBN 0-07-065523-5, (1999). 2. T. Tsukahara, “Design of CMOS RF Circuits,” Maruzen, ISBN: 978-4-621-08203-4, (2009) (in Japanese). |
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| 開講学期 ／Semester |
2017年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Yukihide Kohira |
| 担当教員名 ／Instructor |
Yukihide Kohira, Yasuhiro Hisada |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/30 |
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| 授業の概要 ／Course outline |
Due to the progress of the LSI technology, developing electronics and advancing performance are achieved. Although the speed of a transistor is improved by the progress of the process technology in LSI, it increases the routing delay. Since the routing delay is determined by the layout process, it is important to understand the knowledge about layout design. In this class, students learn the knowledge of the LSI design in advanced process technology. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
1. Students will be able to understand the knowledge of the LSI design. 2. Students will be able to understand how to determine the LSI circuit performance and the power consumption in advanced process technology. |
| 授業スケジュール ／Class schedule |
1. Introduction 2. Review extermination 3. Lecture: CMOS circuits 4. Lecture: Layout design 5, 6. Exercise: CMOS circuit design in transistor level 7, 8. Exercise: Layout design for CMOS circuits 9-15. Presentation: CMOS VLSI circuit design |
| 教科書 ／Textbook(s) |
N. H. E. Weste, D. M. Harris "CMOS VLSI Design: A Circuits and Systems Perspective", Addison Wesley |
| 成績評価の方法・基準 ／Grading method/criteria |
The plan of evaluation is as follows: Attendance: 30% Review examination: 10% Exercise: 30% Presentation: 30% |
| 履修上の留意点 ／Note for course registration |
The following courses are recommended to take in undergraduate. NS4 Semiconductor Devices F4 Logic Circuit Design S6 VLSI Design S7 Advanced Logic Circuit Design |
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| 開講学期 ／Semester |
2017年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Hiroshi Saito |
| 担当教員名 ／Instructor |
Hiroshi Saito, Yukihide Kohira |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/29 |
|---|---|
| 授業の概要 ／Course outline |
Because of advanced deep sub-micron technology in VLSIs, many functions can be implemented on a chip (integrated circuit). Such a chip integrates more than ten millions or hundred millions of transistors. To implement such a chip, it is impossible to design in manual. Recently, most of VLSIs is designed using electronic design automation (EDA) tools. For example, once designer specifies the model of an application using a hardware description language (HDL) with a set of design constraints which consider design requirements, EDA tools automatically synthesize a design from the model which satisfies design requirements. Therefore, it is indispensable for designers to understand the knowledge of EDA tools. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
This course focuses on design automation techniques used in lower level of designs. Lower level in this course means the design from the structural model of a circuit using an HDL to the layout design before the chip fabrication. In addition, this course provides an exercise using EDA tools. Students design layout of a circuit from a structural model of an application specified by Verilog HDL. |
| 授業スケジュール ／Class schedule |
1. Introduction 2. About exercise 1 3. Verilog HDL 4. Overview of logic synthesis 5. Optimization for logic functions 6. About exercise 2 7. Technology mapping and optimization for sequential circuits 8. Verification 9. Exercise 10. Testing and power optimization 11. Layout synthesis 1 12. Layout synthesis 2 13. Exercise 14. Presentation 15. Presentation In the exercise, students create an application such as a signal processing algorithm using Verilog HDL. Then, students synthesize a logic design and a layout design for the Verilog HDL model using Cadence RTL Compiler and Encounter Digital Implemenattion. In addition, students verify the timing requirements and the functionalities for the synthesized layout design using EDI Timing System and Incisive. Finally, students evaluate performance and area of the designed circuit with the consideration for design optimization. Taking with Electronic Design Automation for System-level Design, students can study a standard design flow used in the industry from the functional model of an application by SystemC to the layout design before the chip fabrication. |
| 教科書 ／Textbook(s) |
Not assigned |
| 成績評価の方法・基準 ／Grading method/criteria |
Exercise (85%) and Attendance (15%) |
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| 開講学期 ／Semester |
2017年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Abderazek Ben Abdallah |
| 担当教員名 ／Instructor |
Abderazek Ben Abdallah, Hiroshi Saito |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/23 |
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| 授業の概要 ／Course outline |
As we build increasingly complex parallel systems (e.g. MCSoCs/MPSoCs) one of the greatest challenges is in providing the interconnection networks that permit the system components to communicate. These must be must be high-performance, scalable, simple to design with and power efficient. Network-on-chip architecture is an increasingly popular and feasible alternative to close the productivity gap and achieve the desired performance. The first part of this course should help the student gain an appreciation of NoC approach. The second part of this course is about advanced design and performance issues of computers, such us Multicore Systems, design alternatives for I/O, direct memory access, etc. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
After taking this course a student will be able to: - Describe what interconnections (NoC, buses) are and describe their role in connecting the major system components. - Identify several approaches to processor implementations. - Describe how a system identifies different sources of interrupts and exceptions. |
| 授業スケジュール ／Class schedule |
-On-chip communication organization ( architecture standards, models for performance exploration, synthesis of on-chip communication architectures, NoC topology, routing, switching strategies) -Processor organization (Branch prediction, Trace cache, Value Prediction, Reliability and availability) -Advanecd design issues in multicore-based embedded system |
| 教科書 ／Textbook(s) |
- Textbook: Multicore Systems-on-Chip: Practical Hardware/Software Design, 2nd Ed., By Abderazek Ben Abdallah, ISBN-13: 978-9491216916, Publisher: Springer, 2013 - Various other materials prepared by the instructor. |
| 成績評価の方法・基準 ／Grading method/criteria |
There will be 3 homework assignments, term project, and a research paper. For the research paper a student will be asked to investigate a current topic in processor architecture, write a short paper on the topic, and present his/her results to the class. |
| 履修上の留意点 ／Note for course registration |
-Parallel Computer Architecture -Computer Architecture and Organization |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Course web page and reference materials will be given during the first lecture. |
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| 開講学期 ／Semester |
2017年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Abderazek Ben Abdallah |
| 担当教員名 ／Instructor |
Abderazek Ben Abdallah, Junji Kitamichi |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/23 |
|---|---|
| 授業の概要 ／Course outline |
Embedded Real-time systems are systems that require timely responses to facilitate their operation or they risk performance degradation or even total system failure. This course introduces the various building blocks and underlying scientific and engineering principles behind embedded real-time systems. It covers the integrated hardware and software aspects of embedded processor architectures, along with advanced topics such as real-time, resource and memory management, and RTOS scheduling. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
1. Learn advanced issues about embedded real-time system design and scheduling. 2. Learn how to program with real-time embedded architecture. 3. Learn and apply real-time principles that are used to drive critical embedded systems. |
| 授業スケジュール ／Class schedule |
Topics covered are: -Embedded architectures (building up to modern embedded processors); - Interaction with devices (buses, memory architectures, device drivers); - Concurrency (software and hardware interrupts, timers); - Real-time principles (multi-tasking, scheduling, synchronization); - Implementation trade-offs, - Profiling and code optimization (for performance and memory); - Embedded software (exception handling, loading, mode-switching,programming embedded systems). |
| 教科書 ／Textbook(s) |
Real-Time Embedded Components and Systems, By Sam Siewert Hardcover: 384 pages Publisher: Charles River Media; 1 edition (June 27, 2006) Language: English ISBN-10: 1584504684 ISBN-13: 978-1584504689 |
| 成績評価の方法・基準 ／Grading method/criteria |
There will be 3 homework assignments, term project, and a research paper. For the research paper a student will be asked to investigate a current topic in real time systems, write a short paper on the topic, and present his/her results to the class. For the term project a student (or a group) will be asked to work on a term project to design a microprocessor-based embedded real-time system. |
| 履修上の留意点 ／Note for course registration |
Knowledge about Embedded Systems, Computer Architecture/organization. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Course web page and reference materials will be given during the first lecture. |
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| 開講学期 ／Semester |
2017年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Junji Kitamichi |
| 担当教員名 ／Instructor |
Junji Kitamichi, Hitoshi Oi |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/25 |
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| 授業の概要 ／Course outline |
In this course, many topics, Pipelining with out-order execution, memory hierachy, instruction/data level parallelism, and so on, which are adopted in the advanced computer architecture, such as high-performance general purpose computers, GPGPUs, embedded processors, are explained. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
In this course, our students understand the computer architecture which keeps evolving and obtain the base for more advanced development of it. They can use the knowledge obtained in this lecture to research at their Lab. |
| 授業スケジュール ／Class schedule |
1-2: Pipelining: Basic and Intermediate Concepts 3-4: Fundamentals of Quantitative Design and Analysis 5-6: Memory Hierarchy Design 7-8: Instruction-Level Parallelism and Its Exploitation 9-10: Data-Level Parallelism in Vector, SIMD, and GPU Architectures 11- : Other topics |
| 教科書 ／Textbook(s) |
Computer Architecture, 5th Edition: A Quantitative Approach by John L. Hennessy & David A. Patterson |
| 成績評価の方法・基準 ／Grading method/criteria |
Reports and/or tests |
| 履修上の留意点 ／Note for course registration |
None |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
CQ出版社 マイクロプロセッサ・アーキテクチャ入門 中森 章 著 |
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| 開講学期 ／Semester |
2017年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Hitoshi Oi |
| 担当教員名 ／Instructor |
Hitoshi Oi, Alexander P. Vazhenin |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/31 |
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| 授業の概要 ／Course outline |
Advanced Operating Systems is one of core courses in the graduate program at the University of Aizu, offered from the 3rd quarter of AY2012. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
This is one of course courses in the graduate program in Computer Science and Engineering at the University of Aizu. The course covers from basic design concepts of the modern operating systems to the case studies in the actual implementations of the operating systems to see how they utilize and manage advanced hardware technologies for newly emerging applications. Topics covered overlap with those in the undergraduate operating systems course. However, it is expected that students understand each topic in more detail and at a higher standard. In the first few weeks, basic concepts of OSs will be reviewed. During this period, students will decide the topics for their reports. In the next few weeks, advanced topics (such as distributed systems) and case studies will be covered. |
| 授業スケジュール ／Class schedule |
Week Topics Remarks 1 Course Introduction Multiprocessors Textbook: Section 8.1 2 Multicomputers Textbook: Section 8.2 3 Virtualization Textbook: Section 8.3 4 Distributed Systems Textbook: Section 8.4 5 Case Study: Linux Overview and Processes Textbook: Sections 10.1 to 10.3 6 Case Study: Linux Memory Management, I/O, File System and Security Textbook: Sections 10.4 to 10.8 7 Advanced Topics and Case Studies TBD 8 Advanced Topics and Case Studies TBD 9 Final exam and Project Presentations TBD |
| 教科書 ／Textbook(s) |
Modern Operating Systems, International Edition, 4/E , by Andrew S. Tanenbaum, 4/E ISBN-10: 013359162X • ISBN-13: 9780133591620, Prentice Hall. (or, Academic papers and articles from technical magazines will also be used as the reading materials. |
| 成績評価の方法・基準 ／Grading method/criteria |
The final course grade will be a combination of written exam(s), term paper (or project) and class participation. Letter grades will follow the University Standard (A >= 80, B >= 65, C >= 50). |
| 履修上の留意点 ／Note for course registration |
B or better grades for the Computer Architecture and Operating Systems courses in undergraduate program (or equivalent). C programming proficiency. Understanding and familiarity to *nix concepts and operations. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
The information on this page is subject to change. For the up to date information, please refer to the course web page: http://web-ext.u-aizu.ac.jp/~hitoshi/COURSES/AOS/ and course notice board: http://cnotice.oslab.biz/ |
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| 開講学期 ／Semester |
2017年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Naohito Nakasato |
| 担当教員名 ／Instructor |
Naohito Nakasato |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/31 |
|---|---|
| 授業の概要 ／Course outline |
The course focuses on the advanced theoretical methods for designing of the application-specific parallel algorithms and massively parallel architectures. The systematic design and complexity analysis of parallel algorithms and array processors for some fundamental problem of the linear algebra, graph theory and digital signal processing will be given. At the end of the course the student should be able to: * understand of current trends in the field of application-specific parallel algorithms/architectures; * know how a formal approach can be used to design VLSI-oriented array processors. * know how to project optimal computer architectures for some fundamental algorithms. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
This course will cover (but not limited to) the following contents: VLSI architecture design principles, massively parallel algorithms and array processors, systematic approach to design of application-specific algorithm/architectures, software tools for algorithms/architecture co-design, array processors for fundamental problems of the linear algebra, digital signal processing, graph theory. |
| 授業スケジュール ／Class schedule |
The course will cover the following topics: 1. Introduction to VLSI Architecture: Design Principles and Limitations 2. Massively Parallel Array Processors 3. Systematic Approaches to Design of Application-Specific Algorithm/Architectures 4. Data Dependence Analysis of the Algorithms 5. Regularization and Localization of the Computations 6. Space-Time Mapping of the Algorithms onto Array Processor Space 7. Synthesis of the Optimal Solutions 8. Software Tools for Automatic Design: Introduction to the S4CAD System 9. First Project Presentation 10. Design and Analysis Array Processors for Linear Algebra Problems: o Matrix-matrix multiplication o LU decomposition o Matrix inversion, o Singular Value Decomposition 11. Design and Analysis Array Processors for the Algebraic Path Problem: o Transitive Closure o All-Pairs Shortest Paths o Critical Path o Minimum Spanning Tree o Maximum Reliability Paths 12. Design and Analysis Array Processors for Multidimensional Digital Signal Processing o Discrete Fourier Transform o Discrete Cosine Transform 13. Second Project Presentation |
| 教科書 ／Textbook(s) |
* Kung S.Y. VLSI Array Processors, Prentice Hall, 1987 * Various materials prepared by the instructor |
| 成績評価の方法・基準 ／Grading method/criteria |
Student evaluation method * Project Report (50 points) * Presentation (30 points) * Quizzes and class activity (20 points) |
| 履修上の留意点 ／Note for course registration |
Students are assumed to have taken undergraduate courses that covered basics of the algorithms, data structures and computer architecture: * “Algorithms and Data Structures” * “Advanced Algorithms” * “Computer Organization and Design” The followings are not prerequisite but important. Taking these courses is highly recommended. * “Parallel Computer Architecture” * “VLSI Design” |
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| 開講学期 ／Semester |
2017年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Toshiaki Miyazaki |
| 担当教員名 ／Instructor |
Toshiaki Miyazaki |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/25 |
|---|---|
| 授業の概要 ／Course outline |
Reconfigurable Computing (RC) is some mechanisms with highly flexible computing fabrics such as PLDs/FPGAs (Programmable Logic Devices/Field Programmable Gate Arrays), in order to realize low-cost and high-performance custom solvers suitable for given problems. The principal difference compared to using ordinary microprocessors is the ability to make substantial changes to the datapath itself in addition to the control flow. From this point of view, RC is often called "Field-Programmable Custom Computing Machines (FCCMs)." To realize RC, we have to provide a software or CAD (Computer Aided Design) environment as well as hardware equipment utilizing FPGAs. In this course, the students will learn an overview of the RC concept first, and then hardware and software technologies needed to realize RC. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
・To understand the RC concept ・To learn PLDs/FPGAs ・To learn CAD tools and their algorithms needed to RC ・To know RC examples and applications |
| 授業スケジュール ／Class schedule |
-Programmable Logic Devices (PLDs): structures and variations based on the device technologies -CAD environment and algorithms for PLDs: Technology mapping, place & route, logic partitioning -High-level synthesis and algorithms: mapping software into hardware -RC Architectures -Parallel processing in RC -Reconfigurable computing: Case study (1) -Reconfigurable computing: Case study (2) -Dynamic reconfigurable devices and parallel processing utilizing them -Related device technologies: Course-grain FPGAs and Configurable Processors -Report and presentation from the students |
| 教科書 ／Textbook(s) |
Original handouts and materials will be distributed via WEB site. The detail information will be announced at the first lecture. |
| 成績評価の方法・基準 ／Grading method/criteria |
Homework (30%), Report & Presentation (50%), Attendance & Discussion (10%) |
| 履修上の留意点 ／Note for course registration |
Basic knowledge of the following fields is needed; Logic Circuits, Computer Architecture, and Hardware Description Language (HDL), e.g., Verilog-HDL, VHDL |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
References -Scott Hauck, Andre DeHon Edt., “Reconfigurable Computing: The Theory and Practice of FPGA-based Computation,” Publisher: Horgan Kaufmann Publishers, 2007; ISBN: 978-0-12-370522-8 -Maya B. Gokhale, Paul S. Graham "Reconfigurable Computing : Accelerating Computation with Field-Programmable Gate Arrays" Publisher: Springer, 2005; ISBN: 0387261052 -Patrick Lysaght, Wolfgang Rosenstiel Edt., "New Algorithms, Architectures and Applications for Reconfigurable Computing", Publisher: Springer, 2005; ISBN: 1402031270 -末吉敏則，天野英晴 編, "リコンフィギャラブルシステム," オーム社, 2005; ISBN:427420071X (in Japanese) -Wayne Wolf, "FPGA-Based System Design" Publisher: Prentice Hall, 2004; ISBN:0-13-142461-0 |
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| 開講学期 ／Semester |
2017年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Hitoshi Oi |
| 担当教員名 ／Instructor |
Hitoshi Oi |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/31 |
|---|---|
| 授業の概要 ／Course outline |
This is a project-oriented course to learn and experiments in design and implementation techniques of modern computer systems (Formerly offered as "Advanced Computer Architecture" by 2011). |
| 授業の目的と到達目標 ／Objectives and attainment goals |
This is a project-oriented course to learn and experiments in design and implementation techniques of modern computer systems. Students are requsted to discuss with the instructor on his/her project topics prior to the registration. The student reports in the past years are available upon request. |
| 授業スケジュール ／Class schedule |
In the first few weeks, the related topics will be reviewed using reading materials such as journal/conference papers and magazine articles. Possible topics and tools that can be used for the projects will be introduced during this period. For the rest of the quarter, in addition to the literature study, students will report the progress of their project. Some tools can be used on the workstation provided by the school, but some others will require root access (privileged). Since this is a graduate course, you should have access to the computer in your lab for such tools. The instructor will assist student who have difficulties in using such tools. |
| 教科書 ／Textbook(s) |
Selected journal and conference papers and magazine articles will be used. No textbook required. However, the following book is recommended as a reference: COMPUTER ARCHITECTURE, A Quantitative Approach, Fourth Edition. ISBN-13: 978-0-12-370490-0, ISBN-10: 0-12-370490-1, MORGAN KAUFFMAN . |
| 成績評価の方法・基準 ／Grading method/criteria |
Grading Scheme and Policies Project report (60%) + Presentation (20%) + Class Participation (20%) (tentative). |
| 履修上の留意点 ／Note for course registration |
- Undergraduate Computer Architecture, and Operating Systems (B or better). - Proficiency in *nix and C language. YOU NEED TO DISCUSS YOUR TOPIC WITH THE INSTRUCTOR. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
The contents of this page are subject to change. For up to date information, please refer to the following pages and contact the instructor. http://www.u-aizu.ac.jp/~hitoshi/COURSES/SCA/ http://cnotice.oslab.biz/ |
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| 開講学期 ／Semester |
2017年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Irina I. Khmyrova |
| 担当教員名 ／Instructor |
Irina I. Khmyrova |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/02/06 |
|---|---|
| 授業の概要 ／Course outline |
Overview of communication systems, light and electromagnetic waves, optical fibers, lasers, LED, photodetectors, receivers, optical fiber communication systems. Fundamental principles of optical communications systems and fiber optic communication technology. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
To introduce students to various components of optical communication systems (their strength, operation principles, and limiting factors), and to analyze complete opto-electronic and optical communication systems. |
| 授業スケジュール ／Class schedule |
1. Introduction, motivation for the course, overview of the course content. 2. Elements of Ray and Wave Optics. 3. Interaction of Light with Matter. 4. Optical Waveguides: Fibers. 5. Optical Spectral Filters, Gratings, and Demultiplexers. 6. Review of junction theory in semiconductors 7. Light Sources (Light Emitting Diodes and Lasers) and Modulators (two lectures). 8. Photodetectors (two lectures). 9. Other Optical Components. 9. General Design of Optical Fiber Communication Systems and System Performance. 10. Digital Transmission and Coding and Decoding Techniques. 11. Wavelength Division Multiplexing (WDM) Systems. 12. Free Space Optical Communications and Infrared Sensing: Their Features and Applications. |
| 教科書 ／Textbook(s) |
1. B.E.A.Saleh and M.C.Teich "Fundamentals of Photonics" (John Wiley, New York, 1991. 2. P. Bhattacharya "Semiconductor Optoelectronic Devices" (Prentice Hall, Englewood Cliffs, NJ) |
| 成績評価の方法・基準 ／Grading method/criteria |
Final exam |
| 履修上の留意点 ／Note for course registration |
"Introduction to Optoelectronics" and "Semiconductors" |
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| 開講学期 ／Semester |
2017年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Yasuhiro Hisada |
| 担当教員名 ／Instructor |
Yasuhiro Hisada |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/31 |
|---|---|
| 授業の概要 ／Course outline |
This introductory course in analog VLSI design covers the fundamentals of circuit theory, small signal modeling of bipolar and MOS transistors, bipolar and MOS analog circuit design, single-stage and multi-stage amplifier design, and operational amplifier design. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
To gain a basic understanding of linear low frequency MOS and bipolar transistor analog circuit design. |
| 授業スケジュール ／Class schedule |
1. Basic circuit theory 2. Bipolar and MOS transistor operating regions 3. Bipolar and MOS small-signal models 4. Biasing the bipolar and MOS transistor 5. Single-stage amplifier design and analysis 6. Multi-stage amplifier design and analysis 7. Differential amplifier design and analysis 8. Operational amplifier design and analysis |
| 教科書 ／Textbook(s) |
・"Analysis and Design of Analog Integrated Circuits", Paul R. Gray and Robert G. Meyer, Third edition, John Wiley Publishers. ・"Applied Electronic Devices and Analog ICs", J. Michael McMenamin, Delmar Publishers. |
| 成績評価の方法・基準 ／Grading method/criteria |
Report (50%) and Final exam(50%) |
| 履修上の留意点 ／Note for course registration |
It is desirable that the student have basic understanding of semiconductor devices, VLSI design, circuit theory, and electronics. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Many reference materials related to a particular lecture topic will be distributed during class. |
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| 開講学期 ／Semester |
2017年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Maxim V. Ryzhii |
| 担当教員名 ／Instructor |
Maxim V. Ryzhii |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/27 |
|---|---|
| 授業の概要 ／Course outline |
The course considers theory and physics of operation of classical and heterostructure quantum semiconductor devices for modern computer and communication systems. The course consists of lectures and discussion seminars. The course work report should be prepared at the end of the course (about 4 pages). |
| 授業の目的と到達目標 ／Objectives and attainment goals |
In-depth understanding of physics and principles of operation of advanced semiconductor devices as elements for modern and future computer and communication systems. |
| 授業スケジュール ／Class schedule |
- Electronic structure of semiconductor materials - Transport of carriers and optoelectronic properties - Semiconductor heterostructures and heterostructure devices - Optoelectronic devices - Quantum electronics devices - Tunneling semiconductor devices - Basic semiconductor technology |
| 教科書 ／Textbook(s) |
1. Kwok K.Ng "Complete Guide to Semiconductor Devices" Additional 2. John G. Webster (editor) "Wiley Encyclopedia of Electrical and Electronics Engineering" vol. 8 |
| 成績評価の方法・基準 ／Grading method/criteria |
Grading is based on the evaluation of weekly homework assignment reports (30%) and course report (70%). |
| 履修上の留意点 ／Note for course registration |
Requirements: - Semiconductor Devices - Quantum Mechanics - Introduction to Optoelectronics |
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| 開講学期 ／Semester |
2017年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Hiroshi Saito |
| 担当教員名 ／Instructor |
Hiroshi Saito |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/01/29 |
|---|---|
| 授業の概要 ／Course outline |
Because of advanced deep sub-micron technology in VLSIs, many functions can be implemented on a chip (integrated circuit). Such a chip integrates more than ten millions or hundred millions of transistors. To implement such a chip, it is impossible to design in manual. Recently, most of VLSIs is designed using electronic design automation (EDA) tools. For example, once designer specifies the model of an application using a hardware description language (HDL) with a set of design constraints which consider design requirements, EDA tools automatically synthesize a design from the model which satisfies design requirements. Therefore, it is indispensable for designers to understand the knowledge of EDA tools. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
This course focuses on design automation techniques used in the upper-level of designs. The upper-level in this course includes modeling of an application using SystemC which is C++ with a class for hardware, and synthesis and verification from the SystemC model to the structural model of a circuit. |
| 授業スケジュール ／Class schedule |
1. Introduction 2. Explanation for exercise 3. Languages for Transaction-level Design and Verification 4. SystemC 5. Overview of TLM-driven Design and Verification Methodology 6. Exercise 7. High-level Synthesis Fundamentals 8. Algorithms used in HLS 9. C-to-Silicon Compiler (CtoS) 10. Application of CtoS 11. Verification Fundamentals 12. TLM-driven Verification Flow 13. Exercise 14. Presentation 15. Presentation In the exercise, students model an application such as a signal processing algorithm using SystemC. Then, students synthesize the structural model of the appliaction using C-to-Silicon Compiler and verify the model using Incisive Simulator. Finally, students evaluate performance and area of the designed circuit with the consideration for design optimization. Taking with Electronic Design Automation for Digital VLSI Implementation, students can study a standard design flow used in the industry from the functional model of an application by SystemC to the layout design before the chip fabrication. |
| 教科書 ／Textbook(s) |
Not assigned |
| 成績評価の方法・基準 ／Grading method/criteria |
Exercise (85%) and attendance (15%) |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Cadence, "TLM-driven Design and Verification Methodology" |
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| 開講学期 ／Semester |
2017年度／Academic Year 前期集中 ／1st Semester Intensi |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Hiroshi Saito |
| 担当教員名 ／Instructor |
Hiroshi Saito, Takei M. (Renesas), Horikoshi K. |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/02/20 |
|---|---|
| 授業の概要 ／Course outline |
Overview Embedded systems are included in recent many equipments. These embedded systems support intelligent control system, preserving safeness, interaction between man and machine, and high performance. In this course, students study basic theory and implementation technique required to develop embedded systems. Because of the availability of embedded system boards, the number of registered students will be restricted to 18. Note that this course is provided in Japanese. The first part is 20% of the classes and the second part is 80% of the classes. Both of them impose reports. Evaluation First report 20% Second report 80% |
| 授業の目的と到達目標 ／Objectives and attainment goals |
- |
| 授業スケジュール ／Class schedule |
- |
| 教科書 ／Textbook(s) |
- |
| 成績評価の方法・基準 ／Grading method/criteria |
- |
| 履修上の留意点 ／Note for course registration |
- |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
- |
| Back |
| 開講学期 ／Semester |
2017年度／Academic Year 前期集中 ／1st Semester Intensi |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
Hiroshi Saito |
| 担当教員名 ／Instructor |
Hiroshi Saito |
| 推奨トラック ／Recommended track |
－ |
| 履修規程上の先修条件 ／Prerequisites |
－ |
| 更新日／Last updated on | 2017/02/14 |
|---|---|
| 授業の概要 ／Course outline |
In embedded systems where CPU performance and memory capacity are restricted, a small Operating System with a real-time kernel is used. In this course, students learn realistic methods of software development using a real-time kernel through experiments. In the first half of the exercises, H8 microcomputer is used. In the latter half, software development is carried out using Field Programmable Gate Array. ※Note that this course is distributed in Japanese. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
本科目は，国内で最も多くのシェアを有するμITRON仕様リアルタイムカーネルについて、サービスコールや内部動作をプログラミング実習で体験的に理解し、リアルタイムプログラミングのスタイルを修得することを目的とする。 ターゲットとしてH8マイコンとFPGAのソフトコアCPUに対するプログラムを行うことによって、最終的に少ないリソースで構成された組込みシステムにおいて、ターゲットが変わった場合でも効率良いソフトウェア開発を行うことができるようになる。 |
| 授業スケジュール ／Class schedule |
1．C言語による組み込みアプリケーション開発環境の構築 2．リアルタイムオペレーティングシステム 3．タスクの生成と起動 4．周期起床 5．タスクのスケジューリングについて 6．メッセージボックス 7．イベントフラグ 8．割込み 9．セマフォ 10．リアルタイムプログラミング手法について 11.FPGAに対するNiosII（CPUコア）システムの実装 12．NiosIIシステムにおける組込みアプリケーションの構築 |
| 教科書 ／Textbook(s) |
1. μITRON4.0仕様 Ver.4.02.00 (社) トロン協会 ITRON仕様検討グループ 坂村健 監修／高田広章 編 2. その他、配布テキスト |
| 成績評価の方法・基準 ／Grading method/criteria |
1.出席（50％） 2.レポートもしくは演習問題の進捗状況（50％） |
| 履修上の留意点 ／Note for course registration |
1.FPGAに関する講義（実習）を受けていない方は、事前にシステム構築に関する簡単な知識を習得しておいてください。 2.講義に必要な資料は当日配布します。 3.課題および提出方法は講義最終日にお知らせします。 4.一コマの履修時間は基本的に通常の履修時間に従いますが、進捗状況により多少変動することがあります。 |