AY 2019 Undergraduate School Course Catalog

Computer Systems

2019/07/22

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開講学期
/Semester
2019年度/Academic Year  4学期 /Fourth Quarter
対象学年
/Course for;
3rd year
単位数
/Credits
4.0
責任者
/Coordinator
Tsuneo Tsukahara
担当教員名
/Instructor
Tsuneo Tsukahara, Yasuhiro Hisada
推奨トラック
/Recommended track
履修規程上の先修条件
/Prerequisites

更新日/Last updated on 2019/02/06
授業の概要
/Course outline
Because CMOS technologies are widely used in modern electronics such as cellular and smart phones, we need advanced knowledge of CMOS circuits. Moreover, recently the demand for mixed-signal CMOS LSIs, including analog and RF (Radio Frequency) circuits, is very rapidly increasing, especially for consumer electronics and communication equipment. This course covers basic CMOS analog circuits design. First, basics of electrical circuits including transient analysis will be reviewed. Then, the load line analysis will be introduced and will be applied to basic MOS amplifiers. From the AC performance analysis, small signal equivalent circuits will be given. Finally, OP amplifier and basics of A/D & D/A converters will be covered.
A hands-on approach is emphasized through laboratory exercises in which the student develops skills using the basic test equipment. Starting from series LC resonant circuits, parallel LC resonant circuits will be covered. Then, MOSFET amplifiers with resistive loads will be covered. The student can also learn close relationship between analog amplifiers and digital inverters observing pulse responses of the MOSFET amplifier. Finally, basic Op amplifier circuits and a low-bit A/D converter will be covered.
授業の目的と到達目標
/Objectives and attainment
goals
The primary goals of this course are:
1. To familiarize the student with the basic laws and theorems used in the analysis of electrical and electronic circuits and in the computation of circuit values.
2. To develop the student’s ability to analyze, construct and test electric and electronic circuits connected in various configurations.
3. To deepen understanding of students on CMOS analog and digital circuits as the mainstream VLSI technology.

Students will be able to:
1. Create a small signal equivalent circuit of a given CMOS analog circuit.
2. Analyze circuit performances such as voltage gain and frequency responses.
8. Understand mechanism of A/D & D/A converters.
授業スケジュール
/Class schedule
Lecture and Experiment classes will be independently provided on different days.

Lectures: 7 times (50 minutes by 4 periods)
1. Review of basic electrical circuits (Thevenin and Norton equivalents, parallel LC circuit)
2. Transient analysis (RC, LRC circuits), Review of semiconductor devices.
3. Bipolar transistor basics, MOSFET basics: DC current, load line analysis, small signal (AC) model, parasitic capacitances of MOSFET, Miller effect.
4. Basic MOS amplifiers (common source, common drain, common gate), frequency responses, MOS composite circuits (active-load amplifier, cascode amplifier, CMOS amplifier).
5. Current mirror, differential amplifier, power amplifiers.
6. OP amplifier and its application circuits.
7. Sampling theorem, sample/hold circuit, basics of A/D & D/A converters.

Experiments: 7 times (50 minutes by 4 periods)
1. LC-resonant circuits and in-depth experiments, sinusoidal-wave extraction from pulse waves using LC resonant circuits (Verifying the Fourier series).
2. Measuring MOSFET I-V curves and DC-transfer-function curves of an MOSFET amplifier using a resistive load (1).
3. Measuring MOSFET I-V curves and DC-transfer-function curves of an MOSFET amplifier using a resistive load (2).
4. Measuring gains and AC-transfer-function curves of an MOSFET amplifier using a resistive load.
5. Measuring gains and AC-transfer-function curves of a CMOSFET amplifier: Understanding close relationship between analog amplifiers and digital inverters.
6. OP amplifier applications: voltage follower, inverting amplifier, adder and subtractor, filter.
7. Low-bit A/D converter
教科書
/Textbook(s)
松澤 昭、「はじめてのアナログ電子回路」(基本回路編)、講談社、ISBN978-4-06-156535-7
成績評価の方法・基準
/Grading method/criteria
Lecture: Terminal Exam (50%)
              Quizzes (10%)
Experiment: Reports (40%)

Note: If a student does not submit quizzes and experiment reports, his or her attendance cannot be approved.  
履修上の留意点
/Note for course registration
Related courses: Semiconductor Devices, CSE Exercise I, Fourier Analysis, Fourier Analysis
参考(授業ホームページ、図書など)
/Reference (course
website, literature, etc.)
[Electric circuits]
1. Schaum's Outline of Electric Circuits, ISBN: 0071393072
2. 安居院、吉村、倉持、「エッセンシャル電気回路」 第2版、森北出版、ISBN978-4-627-73562-0

[Electronic circuits and MOS analog integrated circuits]
3. 松澤 昭、「はじめてのアナログ電子回路」(実用回路編)、講談社、ISBN978-4-06-156545-6
A/D・D/A変換器、アクティブ・フィルタなど
4. 谷口 研二、「CMOSアナログ回路入門」、CQ出版、ISBN4-7898-3037-3
5. B. Razavi、「アナログCMOS集積回路の設計 基礎編」、丸善、ISBN4-621-07220-X
  B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, ISBN-13: 978-0070529038

[Note] The course instructor Tsuneo Tsukahara has practical working experience. He worked for NTT labs for 25 years where he was involved in R&D of semiconductor integrated circuits and LSI chips for communication systems. Based on his experience, he can teach the basics of electronic circuits.


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開講学期
/Semester
2019年度/Academic Year  4学期 /Fourth Quarter
対象学年
/Course for;
3rd year
単位数
/Credits
4.0
責任者
/Coordinator
Junji Kitamichi
担当教員名
/Instructor
Junji Kitamichi, Yuichi Okuyama
推奨トラック
/Recommended track
履修規程上の先修条件
/Prerequisites

更新日/Last updated on 2019/02/04
授業の概要
/Course outline
This course provides students with experience in embedded systems
design. The course introduces issues in upstream design in embedded system
and RTOS for real time systems. There are also weekly laboratory sessions on
design of a microprocessor-based embedded system including one or more
custom peripherals.
授業の目的と到達目標
/Objectives and attainment
goals
To serve as a capstone design course to tie together the computer
engineering curriculum via the design of a complete embedded system
involving multiple communicating components.
授業スケジュール
/Class schedule
1: Introduction
2: Basis of embedded software: Polling and Interrupt
3: Basis of embedded software: Memory mapped I/O
4: Explanation of development environment in Lab.
5: Embedded programming
6: Software development process
7: Real Time OS - Toppers
8: Real Time OS - Time Constraints
9: Real Time OS - Other Functions
10: Real Time OS - Priority Inversion
11-12: Real Time Scheduling
13: Analysis of Schedulability
14: Tests and other topics

The order of some items would be changed.
教科書
/Textbook(s)
Text(s) Materials are based on and modified following book and etc.

1-10,14組込みソフトウェア開発技術の基礎
Edited: NCES人材育成プログラム
https://www.nces.i.nagoya-u.ac.jp/NEP/materials/about.html

11-13: 組み込みシステム開発に役立つ理論と手法
Author: 藤倉 俊幸(Toshiyuki Fujikura)
Edition: 2012
Publisher:CQ出版社
ISBN-10: 0123743974, ISBN-13: 978-0123743978
成績評価の方法・基準
/Grading method/criteria
Final examination (50%), and reports of exercises (50%).
履修上の留意点
/Note for course registration
This course requires the contents of following courses.

Computer Architecture
Operating Systems
参考(授業ホームページ、図書など)
/Reference (course
website, literature, etc.)
Course website and other reference material will be given by the instructor during the first class.   


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開講学期
/Semester
2019年度/Academic Year  3学期 /Third Quarter
対象学年
/Course for;
3rd year
単位数
/Credits
3.0
責任者
/Coordinator
Naohito Nakasato
担当教員名
/Instructor
Naohito Nakasato, Abderazek Ben Abdallah
推奨トラック
/Recommended track
履修規程上の先修条件
/Prerequisites

更新日/Last updated on 2019/02/15
授業の概要
/Course outline
A large change in the computing world has started in the last few years: not only are the fastest computers parallel, but nearly all computers will soon be parallel, because the physics of semiconductor manufacturing will no longer let conventional sequential processors get faster year after year, as they have for so long (roughly doubling in speed every 18 months for many years). So all programs that need to run faster will have to
become parallel programs. As multi-core processors and cluster systems have become ubiquitous, the demand for parallelization methods and technologies is also increasing. Parallel computer architecture is a field related to the development of these methods and computing technologies. Parallelism can be applied to different levels of a computer
system and different challenges and solutions exist.
授業の目的と到達目標
/Objectives and attainment
goals
The objective of this course is to understand the basic knowledge for designing and evaluating parallel computer architectures. The class will focus on understanding the elements that characterize parallel architectures, technical challenges, and possible solutions. Exercises in parallel programming will provide an understanding of parallel architectures through actual programming.
授業スケジュール
/Class schedule
1 Introduction to Parallel Computing
2 On Floating-point Arithmetic
3 Basics on Parallel Computing
4 Performance Evaluation of Parallel Computing
5 Single Process Performance Tuning(1)
6 Single Process Performance Tuning(2)
7 Shared Memory Parallel Computers
8 Distributed Memory Parallel Computers
9 Parallel Algorithm/Architecture Co-Design for Matrix Multiplication
10 Multi-core and Many-core Processors
11 Graphic Processing Units
12 Parallel Applications
13 Future Trends in High Performance Computing
14 Special Lecture
教科書
/Textbook(s)
Lecture slide will be available from our lecture website.
成績評価の方法・基準
/Grading method/criteria
Based on the exercise(50%) and report(50%).
履修上の留意点
/Note for course registration
Based on "Computer Architecture" class.
参考(授業ホームページ、図書など)
/Reference (course
website, literature, etc.)
Website in 2017: http://galaxy.u-aizu.ac.jp/note/wiki/PCA2017


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開講学期
/Semester
2019年度/Academic Year  2学期 /Second Quarter
対象学年
/Course for;
3rd year
単位数
/Credits
2.0
責任者
/Coordinator
Yukihide Kohira
担当教員名
/Instructor
Yukihide Kohira
推奨トラック
/Recommended track
履修規程上の先修条件
/Prerequisites

更新日/Last updated on 2019/02/15
授業の概要
/Course outline
Due to the progress of the LSI technology, developing electronics and advancing performance are achieved. Although the speed of a transistor is improved by the progress of the process technology in LSI, it increases the routing delay. Since the routing delay is determined by the layout process, it is important to understand the knowledge about layout design. In this class, students learn the knowledge of the LSI design.
授業の目的と到達目標
/Objectives and attainment
goals
1. Students will be able to understand the knowledge of the LSI design.
2. Students will be able to understand how to determine the LSI circuit performance and the power consumption.
3. Students will be able to understand how to design, evaluate, and verify LSI circuits by applying LSI design flow from logic synthesis to layout design in CAD tools.
授業スケジュール
/Class schedule
Lecture
1. Introduction
2. Review of semiconductor devices (CMOS Logic)
3. LSI design flow, memory
4. LSI layout design
5. Performance of CMOS circuits
6. Power consumption of CMOS circuits
7. Scaling

Exercise
1-3. CMOS circuit design in transistor level
4-5. Layout design for CMOS circuits (Full custom design)
6-7. Layout design for CMOS circuits (Design automation)
# The slots for lectures and exercises are changed in the progress of lectures.
教科書
/Textbook(s)
牧野 博之,益子 洋治,山本 秀和「半導体LSI技術」共立出版
成績評価の方法・基準
/Grading method/criteria
The plan of evaluation is as follows:
Final examination: 60%
Exercises: 40%
Additionally, if a student is absent, the final score is reduced.
履修上の留意点
/Note for course registration
Students are required to have the knowledge of the following courses: LI13 CSE Exercise I (L05 CSE laboratories), NS04 Semiconductor Devices and FU04 Logic Circuit Design (F04 Logic Circuit Design).
参考(授業ホームページ、図書など)
/Reference (course
website, literature, etc.)
Reference
國枝 博昭「集積回路設計入門」コロナ社


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開講学期
/Semester
2019年度/Academic Year  2学期 /Second Quarter
対象学年
/Course for;
3rd year
単位数
/Credits
3.0
責任者
/Coordinator
Hiroshi Saito
担当教員名
/Instructor
Hiroshi Saito, Yoichi Tomioka
推奨トラック
/Recommended track
履修規程上の先修条件
/Prerequisites

更新日/Last updated on 2019/01/29
授業の概要
/Course outline
In digital integrated circuits such as processors, the almost all design starts from modeling functional requirements using a hardware description language (HDL). A circuit is synthesized from the model by using electronic design automation (EDA) tools. Therefore, it is important to know how to model functional requirements using an HDL and how EDA tools synthesize digital integrated circuits.
授業の目的と到達目標
/Objectives and attainment
goals
This course is an advanced course for logic circuit design. In lectures, students study a modeling method for digital integrated circuits using an HDL, the overview of logic synthesis tool, and a verification method for the designed circuits. In exercises, students model circuits using an HDL, synthesize logic circuits using an EDA tool. In addition, students implement the designed logic circuits on a field programmable gate array (FPGA). The performance of the implemented circuits is evaluated on an FPGA board.
授業スケジュール
/Class schedule
Lectures (50 min)
1. Electronic Design Automation
2. Verilog Hardware Description Language (Verilog HDL)
3. Modeling of circuits using Verilog HDL
4. Overview of logic synthesis 1
5. Overview of logic synthesis 2
6. Two-level logic minimization
7. Multi-level logic optimization
8. Technology mapping
9. Logic synthesis for FPGAs
10. Sequential circuit synthesis
11. Logic verification and static timing analysis
12. Power optimization and design for testability
13. Summary
14. Others

Exercises (100 min)
1. How to use Altera Quartus Prime?
2. How to use ModelSim-Altera?
3. How to use TimeQuest Timing Analyzer and PowerPlay Power Analyzer?
4. Modeling and synthesis of combinational circuits using Verilog HDL
5. Modeling and synthesis of memory logics
6. Modeling and synthesis of a counter and implementation on an FPGA
7. Modeling and synthesis of a counter and implementation on an FPGA
8. Modeling and synthesis of a counter and implementation on an FPGA
9. Modeling and synthesis of a counter and implementation on an FPGA
10. Modeling and synthesis of the MIPS processor
11. Modeling and synthesis of the MIPS processor
12. Modeling and synthesis of the MIPS processor
13. Modeling and synthesis of the MIPS processor
14. Modeling and synthesis of the MIPS processor
教科書
/Textbook(s)
Not assigned
成績評価の方法・基準
/Grading method/criteria
Reports (45%) and final examination (55%)

No re-examination
履修上の留意点
/Note for course registration
Logic circuit design should be studied in advance.


Responsibility for the wording of this article lies with Student Affairs Division (Academic Affairs Section).

E-mail Address: sad-aas@u-aizu.ac.jp