AY 2026 Graduate School Course Catalog AY 2026 Graduate School Course Catalog AY 2026 Graduate School Course Catalog
| 2026/02/19 |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
OI Hitoshi |
| 担当教員名 ／Instructor |
OI Hitoshi |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/02/06 |
|---|---|
| 授業の概要 ／Course outline |
This is a project-oriented course to learn and experiments in design and implementation techniques of modern computer systems (Formerly offered as "Advanced Computer Architecture" by 2011). Due to the nature of being project-oriented and fast pace of quarter system, this course is not recommended for the first time (fresh) graduate students unless (a) he/she has discussed with the instructor on the project topic, or (b) he/she has a concrete topic for the project topic. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
This is a project-oriented course to learn and experiments in design and implementation techniques of modern computer systems. Students are requsted to discuss with the instructor on his/her project topics prior to the registration. The student reports in the past years are available upon request. |
| 授業スケジュール ／Class schedule |
The course activities should adapt to the number of registered students and their interests, techincal skills and background, and choices of project topics. Week 1 - Course introduction: -- Information on schedule, instructor, grading scheme will be provided. - Course project discussion: -- The instructor will present the potential project topics using research papers and technical articles. -- The tools and utilities that may be used by the students, and sample projects of the past students will be presented for the reference. - Reading article assignments: -- A research paper (e.g. conference paper from ISCA, Micro or ASPLOS) or an article from technical magagine (e.g. IEEE Computer or CACM) will be presented to the students. The instructor will present the bibliographic information and also summarizes first few sections of the paper. The assignment for the rest to the students will be determined in this week. Weeks 2 to 6 - Project progress report -- Issues and technical problems on the project should be reported, and if necessary, the instructor will assist the student to solve the problems. - Reading assignment -- The student assigned for the week will summarize and present the assigned part -- Discussion on the presented topics within the class. Week 7 - Course project presentations |
| 教科書 ／Textbook(s) |
Selected journal and conference papers and magazine articles will be used. No textbook required. However, the following book is recommended as a reference: COMPUTER ARCHITECTURE, A Quantitative Approach, Sixth Edition. ISBN-13: ISBN: 9780128119051, MORGAN KAUFFMAN . |
| 成績評価の方法・基準 ／Grading method/criteria |
Grading Scheme and Policies Project report (60%) + Presentation (20%) + Class Participation (20%, including pop quizes). |
| 履修上の留意点 ／Note for course registration |
- Undergraduate Computer Architecture, and Operating Systems (B or better). - Proficiency in *nix and C language. YOU NEED TO DISCUSS YOUR TOPIC WITH THE INSTRUCTOR. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
The contents of this page are subject to change. For up to date information, please refer to the following pages and contact the instructor. http://www.u-aizu.ac.jp/~hitoshi/COURSES/SCA/ http://cnotice.oslab.biz/ The instructor has more than five years of industrial experiences as an LSI engineer and Computer Architect at Digital Equipment Corporation, ASTEM RI/Kyoto and HAL Computer Systems. |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
HISADA Yasuhiro |
| 担当教員名 ／Instructor |
HISADA Yasuhiro |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/02/10 |
|---|---|
| 授業の概要 ／Course outline |
This introductory course in analog VLSI design covers the fundamentals of circuit theory, small signal modeling of bipolar and MOS transistors, bipolar and MOS analog circuit design, single-stage and multi-stage amplifier design, and operational amplifier design. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
To gain a basic understanding of linear low frequency MOS and bipolar transistor analog circuit design. |
| 授業スケジュール ／Class schedule |
After the assigned presenters give their presentations on the topics below, the instructor provides a detailed explanation. 1,2. Basic circuit theory 3,4. Bipolar transistor operating regions 5,6. Bipolar transistor small-signal models 7,8. MOS transistor operating regions, small-signal models 9,10. Biasing the bipolar and MOS transistor 11,12. Single-stage amplifier design and analysis 13,14. Multi-stage amplifier design and analysis [Preparation and Review] Students are expected to prepare in advance by carefully reviewing the content of their assigned sections so that they can present it effectively. After completing each unit, students must summarize the content and submit a written report. For each unit (approximately four class sessions), an average of 8-12 hours of study time is expected. |
| 教科書 ／Textbook(s) |
・"Analysis and Design of Analog Integrated Circuits", Paul R. Gray and Robert G. Meyer, Third edition, John Wiley Publishers. ・"Applied Electronic Devices and Analog ICs", J. Michael McMenamin, Delmar Publishers. |
| 成績評価の方法・基準 ／Grading method/criteria |
Report(100%) |
| 履修上の留意点 ／Note for course registration |
It is desirable that the student have basic understanding of semiconductor devices, VLSI design, and electronics. |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
RYZHII Maxim V. |
| 担当教員名 ／Instructor |
RYZHII Maxim V. |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
Courses preferred to be learned prior to this course: SY02 Electronics LI13 CSE Exercise I LI14 CSE Exercise II PL05 Computer Languages NS01 Dynamics NS02 Electromagnetism NS04 Semiconductor Devices |
| 更新日／Last updated on | 2026/02/10 |
|---|---|
| 授業の概要 ／Course outline |
Students will study basic principles of semiconductor device modeling techniques, study the software source code based on Ensemble Monte Carlo particle simulation method (with programming work on computers in class). Students will modify and run the software and obtain different characteristics of semiconductor GaAs n-i-n diode. The characteristics of the n-i-n diode, properties of charged electron transport, different aspects of modeling techniques of semiconductor devices will be discussed and illustrated with computer simulations. Work with Fortran+Xmgrace or MATLAB. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
- Basic principles of semiconductor device computer modeling - Ensemble Monte Carlo particle simulation method and its application to semiconductor device modeling - Understanding of different aspects and phenomena of transient electron transport in semiconductor diode (carrier transport, electric field and potential distributions, velocity overshoot effect). - Graphical visualization of the obtained results. |
| 授業スケジュール ／Class schedule |
Lectures and practicum (in computer class), programming work, software modification, running computer simulations. Calculation of n-i-n diode characteristics with the software. Preparation of the obtained results (plots) with plotting software. Particular schedule will depend on the student progress: 1-2. Lectures on theory and methods, introduction and instructions on the device modeling software preparation. 3-10. Lectures on semiconductor device theory and methods, and practicum on device model programming (computer simulations n-i-n diode). 11-14. Practicum on the device simulations. Preparation of plots with results. Preparation of final report. |
| 教科書 ／Textbook(s) |
Tomizawa Kazutaka Numerical Simulation of Submicron Semiconductor Devices |
| 成績評価の方法・基準 ／Grading method/criteria |
Reports (100%) Students should submit a report with results of computer simulations. |
| 履修上の留意点 ／Note for course registration |
Prerequisites: Students should have some experience and knowledge of basic physics (classical mechanics, electricity and magnetism, semiconductor devices, electric circuits) and programming. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
1) Numerical Simulation of Submicron Semiconductor Devices,Tomizawa Kazutaka 富沢一隆/著 , 半導体デバイスシミュレーション CGで可視化するサブミクロンデバイスの世界 978-4-339-00668-1 （4-339-00668-8） 2) Computational physics : FORTRAN version. Steven E. Koonin and Dawn C. Meredith Addison-Wesley, c1990 |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
SAITO Hiroshi |
| 担当教員名 ／Instructor |
SAITO Hiroshi |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/01/28 |
|---|---|
| 授業の概要 ／Course outline |
Due to the advanced of the deep sub-micron technology in VLSIs, many functions can be implemented on a chip (integrated circuit). More than ten millions or hundred millions of transistors are integrated on the chip. To implement the chip, it is impossible to design in manual. Recently, the most of VLSIs is designed using electronic design automation (EDA) tools. For example, once designer specifies the model of an application using a programming language such as C++ with a set of design constraints which consider design requirements, the EDA tools automatically synthesize a design from the model which satisfies the design requirements. Therefore, it is indispensable for designers to learn the EDA tools. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
In this course, students learn the standard design flow in digital VLSIs from a functional model of an application specified in SystemC to the Register Transfer Level (RTL) design of the application. However, it is difficult to design by the knowledge for the design techniques only. Therefore, in this course, students get the skill through an exercise. In the exercise, students design a VLSI circuit based on the standard design flow with the EDA tools. |
| 授業スケジュール ／Class schedule |
1. Introduction 2. Explanation for the exercise 3. SystemC 4. Exercise 5. Tutorial for Stratus 6. Exercise 7. High-level Synthesis (HLS) Fundamentals 8. Exercise 9. Design space exploration using Stratus 10. Exercise 11. Algorithms used in HLS 12. Exercise 13. Presentation 14. Presentation In the exercise, students creates a functional model of an application such as a signal processing algorithm using SystemC. Then, students synthesize the RTL model using a Cadence HLS tool. In addition, students verify the functional requirements using a Cadence logic simulator. Finally, students evaluate the performance and area of the designed circuit. |
| 教科書 ／Textbook(s) |
Not assigned |
| 成績評価の方法・基準 ／Grading method/criteria |
Presentation (55%) and exercise (45%) |
| 履修上の留意点 ／Note for course registration |
Taking with "Electronic Design Automation for Digital VLSIs", students can study the standard design flow used in the industry from the functional model of an application by SystemC to the layout design before the chip fabrication. |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 前期集中 ／1st Semester Intensive |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
SAITO Hiroshi |
| 担当教員名 ／Instructor |
SAITO Hiroshi, TAKEI Masahiko (Maxell), HORIKOSHI Kenichi |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/01/28 |
|---|---|
| 授業の概要 ／Course outline |
Embedded systems are included in recent many devices. These embedded systems support intelligent control system, preserving safeness, interaction between man and machine, and high performance. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
In this course, students study the basic theory and the implementation technique required to develop embedded systems. |
| 授業スケジュール ／Class schedule |
The 1st part: 12 periods (external instructors) ・Analysis of requirements specification ・Overview of real-time OS ・Programming techniques of real-time systems ・Event-driven programming ・Project management and quality management The second part: 2 periods (Prof. SAITO) ・Introduction of a wild animal alert system (an example of IoT system) ・Generation of deep learning model to detect wild animals ・Deployment of the generated model to Raspberry Pi |
| 教科書 ／Textbook(s) |
Not assigned |
| 成績評価の方法・基準 ／Grading method/criteria |
Two reports Report for the first part - 80% Report for the second part - 20% |
| 履修上の留意点 ／Note for course registration |
1. The number of students is restricted to 16 2. Lectures are provided by Japanese because the most of the lectures is provided by external instructors 3. Schedule may be changed by the business of the external instructors |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
External instructors have practical experience. While working at Renesas, they were involved in product planning and development of embedded OS and embedded software. Based on this experience, they teach the basics of embedded systems. Reference: 『図解μITRONによる組込みシステム入門』 (in Japanese) |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
JING Lei |
| 担当教員名 ／Instructor |
JING Lei |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
NA |
| 更新日／Last updated on | 2026/01/23 |
|---|---|
| 授業の概要 ／Course outline |
Wearable Computing devices take more and more concern as they embody the latest research progress across multiple disciplines including IoT, AI, CHI, biomechanics, electronics, and new materials. And Wearable computing is providing the evolutionary changes on several important application fields like VR, healthcare, robotics, and so on. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
This course is a fundamental course to help the students with proper computer science and engineering knowledge to get familiar with this active research field, embedded wearable computing. |
| 授業スケジュール ／Class schedule |
1- Course introduction (Lecture) 2- How to design a wearable computing device (Lecture) 3- How to design a wearable computing device (Exercise) 4- Wearable I/O (Lecture) 5- Wearable I/O (Exercise) 6- Signal Processing (Lecture) 7- Signal Processing (Exercise) 8- Measurement and Estimation (Lecture) 9- Measurement and Estimation (Exercise) 10- Classification and Recognition (Lecture) 11- Classification and Recognition (Exercise) 12- Project integration 1 (Exercise) 13- Project integration 2 (Exercise) 14- Project presentation (Lecture) |
| 教科書 ／Textbook(s) |
Handout |
| 成績評価の方法・基準 ／Grading method/criteria |
Project presentation 40% Project report 40% Attitude 20% |
| 履修上の留意点 ／Note for course registration |
NA |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
NA |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
BEN ABDALLAH Abderazek |
| 担当教員名 ／Instructor |
BEN ABDALLAH Abderazek, DANG Nam Khanh |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/01/30 |
|---|---|
| 授業の概要 ／Course outline |
This course covers brain-inspired (neuromorphic) neural networks that mimic the functional behavior and the organizational structure of the neocortex. We present spiking neurons and explore principles of computation and self-organization in biological and artificial neural networks. The course reviews functional plasticity models and emergent computational capabilities of neural networks, focusing on short-term and long-term synaptic plasticity to develop information-processing devices directly inspired by the working of neurons, synapses, and networks. This should enables the development of novel high-performance neuro-inspired computing platforms. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
After finishing this course, a student will: - Understand the characteristics of neuromorphic circuit elements. - Have a broad overview of the basic principles of neuromorphic computing and the differences with traditional computing paradigms; - Familiarize with state-of-the-art neuromorphic hardware systems, including some hands-on experience with such architectures - Understand learning algorithms for spiking neural networks and the pros and cons of using spiking architectures - Have some experience with neuromorphic algorithm design, complexity analysis, and applications of neuromorphic architectures in event-driven sensors. |
| 授業スケジュール ／Class schedule |
1. Overview of past and present neurocomputing approaches 2. Neuron Models and Coding 3. Hardware Models of Spiking Neurons 4. Synaptic Dynamics 5. Synaptic Plasticity Mechanisms 6. Learning in Neuromorphic Systems 7. Emerging Memory Devices for Neuromorphic Systems 8. Communication Networks for Neuromorphic Systems 9. Fault-Tolerance in Neuromorphic Systems 10 Fault-Recovery and Reliability in Neuromorphic Systems 11 Reconfigurable Neuromorphic Computing System 12. Neuromorphic AI Hardware 13. Synthesizing real-time neuromorphic cognitive systems: Real-world HW-SW Design 1 14. Synthesizing real-time neuromorphic cognitive systems: Real-world HW-SW Design 2 [Pre-Class learning] Read the lecture and exercise materials. If anything is unclear, research it using the textbook or online resources. [Post-Class learning] Read the textbook and lecture materials to deepen your understanding. Complete any assigned tasks. If exercises were not finished during class, finish them and prepare for the report. |
| 教科書 ／Textbook(s) |
Abderazek Ben Abdallah, Khanh N. Dang (Authors), ''Neuromorphic Computing Principles and Organization,'' Publisher: Springer; 1st ed. 2022 edition (March 12, 2022), ISBN-10 : 3030925242, ISBN-13 : 978-3030925246 |
| 成績評価の方法・基準 ／Grading method/criteria |
- Presentations and class activities: 25 % - Home work: 25 % - Final Exam: 50 % |
| 履修上の留意点 ／Note for course registration |
Needed knowledge on: Neural Networks |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Course web page: https://web-ext.u-aizu.ac.jp/misc/neuro-eng/book/NeuromorphicComputing/ |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 1学期 ／First Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
SUZUKI Daisuke |
| 担当教員名 ／Instructor |
SUZUKI Daisuke, KOHIRA Yukihide |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/02/06 |
|---|---|
| 授業の概要 ／Course outline |
Because CMOS technologies are widely used in modern electronics, we need advanced knowledge of scaled CMOS devices. Moreover, recently the demand for mixed-signal LSIs, including analog and RF (Radio Frequency) circuits, is very rapidly increasing, especially for consumer electronics, communication equipments, and hardware accelerators for artificial intelligence (AI) such as deep learning. In addition, knowledge of scaled CMOS devices is also important for designing emerging memories such as MRAMs (Magnetic RAMs) and ReRAMs (Resistive RAMs), and so on. This course concerns theoretical and practical aspects of CMOS devices and modeling. First, fundamentals of semiconductor devices, which are undergraduate level, will be reviewed and distributed-constant circuit models will be also provided. Then, in-depth modeling of MOS transistors will be introduced using the textbook (Chapters 2 to 5). This helps you design VLSIs using the deep sub-micron CMOS in the near future. Finally, design examples of mixed-signal LSIs and emerging memory LSIs will be overviewed. Recent trends in semiconductor LSI are also referred during the class. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
At the end of the course the student should be able to: ・Explain the basic concepts of the semiconductor devices. ・Design CMOS VLSI chips. ・Understand MOS transistor models used for design of mixed-signal LSIs ・Forecast the future direction of VLSI technologies. |
| 授業スケジュール ／Class schedule |
[Course Schedule] 1. Course Content and Format The course consists of 14 lecture sessions, each comprising two 50-minute classes. Each lecture will explain the content of handouts and the textbook, and introduce relevant recent technological developments when appropriate. Lecture Topics: 1. Review of Undergraduate-Level Semiconductor Devices (1) 2. Review of Undergraduate-Level Semiconductor Devices (2) 3. Fundamentals of Distributed-Constant Circuit Models and Thermal Noise 4. Fundamentals of Device Physics (Chapter 2): Focus on MOS Capacitors and High Electric Field Effects (1) 5. Fundamentals of Device Physics (Chapter 2): Focus on MOS Capacitors and High Electric Field Effects (2) 6. MOSFET Devices (Chapter 3) (1) 7. MOSFET Devices (Chapter 3) (2) 8. CMOS Device Design (Chapter 4): Focus on Scaling and Threshold Voltage Variations (1) 9. CMOS Device Design (Chapter 4): Focus on Scaling and Threshold Voltage Variations (2) 10. CMOS Performance Factors (Chapter 5): Basic Circuits and Effects of Parasitic Components (1) 11. CMOS Performance Factors (Chapter 5): Basic Circuits and Effects of Parasitic Components (2) 12. CMOS Performance Factors (Chapter 5): Device Parameters, Delay Time, and Advanced Devices (1) 13. CMOS Performance Factors (Chapter 5): Device Parameters, Delay Time, and Advanced Devices (2) 14. Case Studies of Mixed-Signal LSIs and Emerging Memory LSIs 2. Pre-Class and Post-Class Study [Pre-Class Study] Handouts to be used in lectures will be available in advance via LMS. Students should read the handouts and relevant sections of the textbook before class, identifying parts they understand and those they do not (approx. 1.5 hours per lecture). [Post-Class Study] After each lecture, students should review the handouts and textbook to solidify their understanding (approx. 1.5 hours per lecture). Additionally, a final report assignment will be given to deepen understanding of relevant topics (approx. 18 hours total). |
| 教科書 ／Textbook(s) |
Y. Taur and T. H. Ning, "Fundamentals of Modern VLSI Devices (3rd Edition)", Cambridge University Press, ISBN 978-1108480024, (2021). |
| 成績評価の方法・基準 ／Grading method/criteria |
1. Report: 100% 2. At the end of the course, topics are given to students. They are required to survey and study about the topics by themselves. |
| 履修上の留意点 ／Note for course registration |
The following or related under graduate courses are recommended to take: ・Semiconductor Devices （半導体デバイス） ・VLSI Design （VLSI設計技術） ・Electronics （電子回路） |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
1. T. Tsividis, “Operation and Modeling of the MOS Transistors,” 2nd Edition, ISBN 0-07-065523-5, (1999). 2. T. Tsukahara, “Design of CMOS RF Circuits,” Maruzen, ISBN: 978-4-621-08203-4, (2009) (in Japanese). |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
KOHIRA Yukihide |
| 担当教員名 ／Instructor |
KOHIRA Yukihide, SAITO Hiroshi |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/02/04 |
|---|---|
| 授業の概要 ／Course outline |
Due to the advanced of the deep sub-micron technology in VLSIs, many functions can be implemented on a chip (integrated circuit). More than ten millions or hundred millions of transistors are integrated on the chip. To implement the chip, it is impossible to design in manual. Recently, the most of VLSIs is designed using electronic design automation (EDA) tools. For example, once designer specifies the model of an application using a hardware description language (HDL) with a set of design constraints which consider design requirements, the EDA tools automatically synthesize a design from the model which satisfies the design requirements. Therefore, it is indispensable for designers to learn the EDA tools. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
In this course, students learn the standard design flow in digital VLSIs from a structural model of an application specified in Verilog HDL to the layout design. However, it is difficult to design by the knowledge for the design techniques only. Therefore, in this course, students get the skill through an exercise. In the exercise, students design a VLSI circuit based on the standard design flow with the EDA tools. |
| 授業スケジュール ／Class schedule |
In this course, classes are conducted in two formats: a lecture format for learning about design technologies, and a progress review format in which students present and discuss the progress of exercises carried out individually outside of class hours. 1. Lecture: Introduction 2. Lecture: Explanation for the exercise and Tutorial for EDA tools (1) 3. Lecture: Verilog HDL 4. Lecture: Tutorial for EDA tools (2) 5. Lecture: Logic synthesis (1) 6. Lecture: Logic synthesis (2) 7. Lecture: Layout synthesis (1) 8. Progress review: Review of exercise progress 9. Lecture: Layout synthesis (2) 10. Progress review: Review of exercise progress 11. Lecture: Verification, testing, and power optimization 12. Progress review: Review of exercise progress 13. Progress review: Presentation of exercise assignments 14. Progress review: Presentation of exercise assignments In the exercise, students create a model for an application such as a signal processing algorithm using Verilog HDL. Then, students synthesize a logic design and a layout design from the Verilog HDL model using Cadence tools. In addition, students verify the timing requirements and the functional requirements for the logic design and the layout design. Finally, students evaluate the performance and area of the designed circuit. [Preparation and Review] No advance preparation is required. Including time for reviewing lectures and preparing materials for the progress review, the estimated time required for the exercises is 20 hours for logic synthesis, 30 hours for layout synthesis, and 10 hours for verification and evaluation. |
| 教科書 ／Textbook(s) |
Not assigned |
| 成績評価の方法・基準 ／Grading method/criteria |
Presentation (50%) Exercise (36%) Attitude in classes (14%) |
| 履修上の留意点 ／Note for course registration |
This course assumes that students have basic knowledge and skills in VLSI design. In particular, it is recommended that the students have acquired credits or equivalent knowledge and skills in at least one course among the following courses: SY06 VLSI Design, SY07 Advanced Logic Circuit Design, IE02 Integrated Exercise for Systems II, or SYA08 System-level Design for Digital VLSIs. Taking with SYA08 System-level Design for Digital VLSIs, students can study the standard design flow used in the industry from the functional model of an application by SystemC to the layout design before the chip fabrication. It is recommended to take both SYA08 System-level Design for Digital VLSIs and this course. |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
KITAMICHI Junji |
| 担当教員名 ／Instructor |
KITAMICHI Junji, TOMIOKA Yoichi |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/02/04 |
|---|---|
| 授業の概要 ／Course outline |
In this course, many topics, Pipelining with out-order execution, memory hierachy, instruction/data level parallelism, and so on, which are adopted in the advanced computer architecture, such as high-performance general purpose computers, GPGPUs, embedded processors, are explained. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
In this course, our students understand the computer architecture which keeps evolving and obtain the base for more advanced development of it. They can use the knowledge obtained in this lecture to research at their Lab. |
| 授業スケジュール ／Class schedule |
[Lecture] 1: Introduction 2: Basic Concepts of Processor: In-order pipeline 3: Basic Concepts of Processor: Interrupt 4: Basic Concepts of Processor: Memory mapped I/O 5: Fundamentals of Quantitative Design and Analysis 6: Memory Hierarchy Design 7: Instruction-Level Parallelism: Basic 8: Instruction-Level Parallelism: Out of Order Pipeline 9: Data-Level Parallelism in Vector and SIMD Architectures 10: Data-Level Parallelism in GPU Architectures 11: Thread-Level Parallelism: Multi-core Processor 12: Thread-Level Parallelism: Cache system for Multi-core Processor 13-14 : Other topics [Exercise] Depending on the instructor, homework may be assigned during the lecture. [Pre-class Learning] It is recommended that you review the contents of computer architecture in undergraduate classes. The total time required for pre-class learning is 20 hours. [Post-class Learning] Review the contents of the lecture, especially the terminology, and make sure you understand and remember them. The time required for post-class learning is 3 hours per lecture. |
| 教科書 ／Textbook(s) |
2-4: Computer Organization and Design MIPS Edition 5-14: Computer Architecture, 6th Edition: A Quantitative Approach |
| 成績評価の方法・基準 ／Grading method/criteria |
Mini Reports (40%) and exam. (60%) |
| 履修上の留意点 ／Note for course registration |
None For undergraduate students, they should get the credits of Computer Architecture and Embedded Systems. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
CQ出版社 マイクロプロセッサ・アーキテクチャ教科書 中森 章 著 |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
OI Hitoshi |
| 担当教員名 ／Instructor |
OI Hitoshi, MATSUMOTO Kazuya |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
- B or better grades for the Computer Architecture and Operating Systems courses in undergraduate program (or equivalent). - C programming proficiency. - Understanding and familiarity to *nix concepts and operations. |
| 更新日／Last updated on | 2026/02/06 |
|---|---|
| 授業の概要 ／Course outline |
This course has a set of clearly and explicitly defined prerequisites. If you cannot provide official documents that support your meeting the prerequisites (most typically, undergrad transcripts), PLEASE DO NOT REGISTER. Registration from such students will be declined. If you do not have necessary technical/academic backgrounds, but still want to take this course, please take appropriate conversion courses first. Advanced Operating Systems is one of core courses in the graduate program at the University of Aizu, offered from the 3rd quarter of AY2012. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
This is one of core courses in the graduate program in Computer Science and Engineering at the University of Aizu. The course covers from the basic design concepts of the modern operating systems to the case studies in the actual implementations of the operating systems to see how they utilize and manage advanced hardware technologies for newly emerging applications. Topics covered overlap with those in the undergraduate operating systems course. However, it is expected that students understand each topic in more detail and at a higher standard. |
| 授業スケジュール ／Class schedule |
Since the course is scheduled to meet once a week, the course activity is described on a weekly- basis below. For the lecture part of the class, we use the sections of Chapter 10 (Case Study 1: Unix, Linux and Android) of the textbook as specified below. We also utilize the first six chapters of the textbook for reviewing the undergraduate operating systems course. Week 1 - Introduction to the course - Course schedule, textbook, grading scheme - Course project -- Types of project: -- Experiments, -- Research paper/article summary -- Source code analysis -- past project topics -Reading Assignments -- Bibliographic information of the paper/article selected by the instructor. -- Overview and summary of first few sections by the instructor. -- Assignment of remaining part to the students and their schedule. -Lecture topics of the week: Unix/Linux history (Textbook Section 10.1) - Quiz to review the understanding of prerequisite courses (operating systems and computer architecture) Preparation before the class (p) /Review after the class (r) - Retrieve course materials used in the undergraduate OS and architecture classes. (p) - Section 10.1 presented in the class (r) - Read the article (r) and summary the assigned part if schedule for the next week (p) - Consider the potential project topics with the information provided by the instructor and also literature/internet search (r). Course activities for Weeks 2 to 6 From the 2nd week to the 6th week, we will cover the topics specified as below with the activities include: - Quiz for reviewing the undergraduate-level understanding of the topics. - Lecture using the corresponding section of the textbook. - Summary presentation of the reading assignment by the student assigned and the discussion on the topics - Course project progress report and consultation with the instructor Preparation and review tasks common to Weeks 2 to 6 - Review the topics of the week with the undergraduate OS courses - Read the section in the textbook corresponding to the topics of the week. - Read the article provided by the instructor. Summarize the assigned part for the presentation at the next class meeting. Review the part presented by other students in the class. Week 2 - Lecture topics of the week: Linux overview (Section 10.2). - Corresponding undergraduate material: Chapter 1 (Introduction). - Students are expected to decide the course project topics this week. Week 3 - Lecture topics of the week: Processes, threads and scheduling (Section 10.2). - Corresponding undergraduate material: Chapter 2 (Processes and threads). Week 4 - Lecture topics of the week: Memory Management. - Corresponding undergraduate material: Chapter 3 (Memory Management) Week 5 - Lecture topics of the week: Input/Output. - Corresponding undergraduate material: Chapter 5 (Input/Output). Week 6 - Lecture topics of the week: Fif Systems. - Corresponding undergraduate material: Chapter 4 (File systems). Week 7 - Project presentation - Final Exam |
| 教科書 ／Textbook(s) |
Modern Operating Systems, Global Edition, 5/E* , by Andrew S. Tanenbaum, ISBN 13: 9780137618873 (or 9780137618880for eTextbook) Prentice Hall. This is a REQUIRED textbook. Please contact the instructor for text purchasing options. Academic journal (e.g. IEEE Transactions on Computers) and conference (e.g. ASPLOS) papers and articles from technical magazines (e.g. IEEE Micro) will also be used as the reading materials. |
| 成績評価の方法・基準 ／Grading method/criteria |
The final course grade will be a combination of written exam(s) (40%), term paper (or project) (40%) and class participation (20%). There will be pop quizes and they will also be taken into the final grade (will be part of participation points of 20%). Letter grades will follow the University Standard (A >= 80, B >= 65, C >= 50). |
| 履修上の留意点 ／Note for course registration |
PLEASE READ THIS PART CAREFULLY. Especially if your undergraduate major is not in the computer science/engineering. If you cannot provide official documents that support your meeting the prerequisites (most typically, undergrad transcripts), PLEASE DO NOT REGISTER. - B or better grades for the Computer Architecture and Operating Systems courses in undergraduate program (or equivalent). For the undergraduate OS, it should cover the Chapters 1 to 6 of the Modern Operating Systems (or equivalent). - C programming proficiency. - Understanding and familiarity to *nix concepts and operations. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
The instructor has more than five years of industrial experiences as an LSI engineer and Computer Architect at Digital Equipment Corporation, ASTEM RI/Kyoto and HAL Computer Systems. The information on this page is subject to change. For the up to date information, please refer to the course web page: http://www.u-aizu.ac.jp/~hitoshi/COURSES/AOS/ |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
1st year , 2nd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
TOMIOKA Yoichi |
| 担当教員名 ／Instructor |
TOMIOKA Yoichi, OKUYAMA Yuichi |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
－ |
| 更新日／Last updated on | 2026/02/04 |
|---|---|
| 授業の概要 ／Course outline |
Deep learning models such as neural networks are used in research and development for a wide variety of systems, including automotive, medical, and surveillance systems. Because the training of deep learning models requires a large amount of computation, it is essential to exploit the performance of Central Processing Units (CPUs), Graphics Processing Units (GPUs), and other dedicated circuits to accelerate training. That also requires numerical computation libraries and virtual environments. In this lecture, students will learn about the numerical libraries and virtual environments necessary for deep learning research and development and acquire skills to build an environment for deep learning research and development. Students will also learn the knowledge and techniques required to accelerate inference. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
1. Students will acquire knowledge and abilities to set up an environment for deep learning research and development. 2. Students will acquire knowledge for accelerating deep learning training and realizing efficient deep learning models. |
| 授業スケジュール ／Class schedule |
Exercises 1, 2, and 3 are conducted in a hands-on exercise format. All other classes are conducted in a lecture format. 1-2. Deep Learning Environments & Virtual Machines (Cloud & Local Resource) 3-4. Execution Mechanism of Deep Learning Frameworks 5-6. Exercise 1: Environment Setup for Deep Learning Training 7-8. Deep Learning Acceleration and Performance Evaluation 9. Exercise 2: Deep Learning Acceleration & Evaluation 10-11. Model Compression 12. Neural Network Optimization 13-14. Exercise 3: Model Optimization Pre-class study (1 hour × 14 classes) Carefully read the lecture and exercise materials to understand the overall flow and review key terminology. Post-class study Exercise 1 Part 1 and Part 2, and Exercise 2: Work on the exercise assignments and prepare reports (5 hours × 3 classes). Exercise 3: Work on the exercise assignment and prepare a report (6 hours). Lectures: Review lecture materials and implement and evaluate sample code to deepen understanding (3 hours × 9 classes). |
| 教科書 ／Textbook(s) |
No textbook. |
| 成績評価の方法・基準 ／Grading method/criteria |
Report 100% |
| 履修上の留意点 ／Note for course registration |
No special prerequisite. Students should have basic knowledge of Linux/Unix command line and Python programming. You must be able to agree to the following two points 1. You must create a Google account. 2. In case of shortage of computing units, you must subscribe to Google Colab Pro (1,179 yen/month as of January 2025). |