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- Victor I. Varshavsky,
- Professor, Computer Logical Design Laboratory
Main results obtained in 1993:
- two-level structure of asynchronous array global synchronization
with one rhythm driver is suggested
- a technique of self-timed device synthesis by synchronous Mealy
automata specification is developed
- new methods of direct event specification translation are
developed
- several buses using a new efficient current sensor
are designed
- some results are obtained in reducing arbitrary faults to
stuck-at ones