Computer Architecture Laboratory

/ Masatoshi Shima / Professor
/ Robert H. Fujii / Associate Professor
/ Wanming Chu / Research Associate

Computer Architectrue Laboratory is organized with 3 faculty members. The followings are the summary of each member.

1. Prof. Masatoshi Shima:

   Research:

   a. RTL Cell Library for Data Path
   b. Standardization of VerilogHDL Programming for Control Path
   c. Multi Cycle MIPS Processor RTL Model
   d. Pipeline MIPS Processor RTL Model
   e. Test Program for MIPS Processor
   f. Cycle Acculate Modelig by C++ for Multiplication and Division
   

   Teaching:

   I taught Computer Architecture, Operating System and the laboratory of Computer Architecture. I developed and updated multicycle MIPS processor RTL model and its system RTL model. Following teaching materials are available as hard copies:

   a. Introduction to Microprocessor
   b. Introduction to Processor Design
   c. Logic Design for Microprocessor
   d. Functional Specification of MIPS Processor to be designed
   e. RISC Processor
   f. Mini Computer
   g. Multi Cycle MIPS Processor Design
   

   Following laboratories handouts are prepared and available at file:///home/course/comparch/index/index.html

   a. Introduction to Cadence System for Microprocessor Design
   b. File System
   c. Introduction to Schematic Entry
   d. Schematic Entry of Multi Cycle MIPS Processor
   e. Schematic Entry of ALU
   f. Simulation Method
   g. How to Use Testbench
   h. VerilogHDL Programming Method
   i. Test Program Generation
   

2. Prof. Robert H. Fujii:

   This year's activities have included the design of a microcontroller controlled motorized wheelchair prototype, the design of a fuzzy logic controller using Verilog, and the design of a high speed pipeline control unit using Verilog. Implementation of the motorized wheelchair prototype into a real system which can be ridden by people with disabilities is being carried out. Analog circuit designs of various modules will be forthcoming.

3. Prof. Wanming Chu:

   Research:

   • Parallel Multithreaded Architecture
     Processor performance can be improved by executing as many instructions as possible in every clock cycle. We have examined various design issues of the parallel multithreaded architecture. We are working on the improving processor performance with horizontal multithreading technique.

   • Multi-port Memory based Interconnection Network
     In this project, we investigated the structure of the mailbox-oriented Interconnection network (IN) for message passing parallel system.In order to achieve high throughput and low communication latency, we examined static, dynamic, and combined mailbox allocation strategies. We developed a simulator in C++ and Java to compare the overhead and bandwidth of the 9 allocation strategies, and also compare them to those of traditional interconnection networks. Our simulation results show that the throughput provided by the mailbox-oriented IN can reach dozen of Gbps which satisfies many practical applications.

Refereed Journal Papers

1. Kenji Watanabe, Wanming Chu, and Yamin Li. Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading. Australian Computer Science Communications, vol. 23, No. 4, pp. 122-129, 2001.

1. Wanming Chu, and Yamin Li. Allocation Strategies and Performance Simulation of Communication Buffers. Proceedings of the 4th World Multiconference on Systemics, Cybernetics and Informatics, Volume IV, Communications Systems and Networks, pp. 15-20, IIIS, International Institute of Informatics and Systemics, July 2000.

1. Inoue, T., Graduation Thesis: Robot Position Recognition Utilizing Color Difference Information. University of Aizu, 2001, Thesis Advisor: R. H. Fujii.

2. Kirino, A., Graduation Thesis: Design and Analysis of a CMOS Operational Amplifier. University of Aizu, 2001, Thesis Advisor: R. H. Fujii.

3. Tanno, Y., Graduation Thesis: Design of an Audio Amplifier with Discrete Transistors. University of Aizu, 2001, Thesis Advisor: R. H. Fujii.

4. Hoshi, R., Graduation Thesis: Motor Control for an Autonomous Mobile Wheelchair, University of Aizu, 2001, Thesis Advisor: R. H. Fujii.

5. Igarashi, S., Graduation Thesis: Control of Sensors and Stepper Motor for a Motorized Wheelchair. University of Aizu, 2001, Thesis Advisor: R. H. Fujii.

6. Iijima, J., Graduation Thesis: Research on the Use of Sensors for a Powered Wheelchair. University of Aizu, 2001, Thesis Advisor: R. H. Fujii.