In 2001, research themes of the laboratory was On-Chip Learning Artificial Neuron, Logical Timing and Decentralized Control in Massively Parallel Computing Systems and Noise Immunity Asynchronous Protocols with Postponed Handshake.

In the first theme the problem of design floating gate transistors based on-chip learning artificial neural networks were studied. Design methodology of such a structure is created. The methodology could be used for circuit optimization taking into account elements parameter and dimension deviations. Especially important problemis the tolerance to supply voltage deviations, because of possible difference in the voltages in learning and working phases. As a result of investigation the main parts of the structure and their design methodology had been developed. The proposed structure is fully tolerant to any kind of deviations and especially efficient in the environment where supplied voltage varies greatly. The tolerance of the structure was reached using the idea of compensating deviations in one part of the structure by deviations in another part. Such an approach is important because technology process is going to smaller design rules and supply voltage. The possibility of using ??oating gate transistors based step voltage comparator as a way to refresh synapse weight represented as a voltage in dynamic memory is shown.

In the second theme, we studied the problems of increasing functional power of beta-driven CMOS arti??cial neurons along with the ways of increasing their implementability. The following results were obtained:

• A special class of threshold functions (Horner's functions) was suggested as test functions for learning of neurons. It was shown that Horner's functions have the complexity close to maximum and have the minimum length of checking sequences that is very important for experiments with neuron learning.
• The beta-driven artificial neuron learnable to non-isotonous threshold functions was studied. We suggested the neuron that have synapses capable to form the weight and type (excitatory or inhibitory) of the input during the learning, using only increment and decrement signals. A neuron with such synapses can be learned to an arbitrary threshold function of a certain number of variables.
• For such kind of neuron synapse circuits are suggested with one and two memoryelements for storing positiveand negative inputweights. The results of SPICE simulation prove that the problem of teaching neuron to non-isotonous threshold functions has stable solutions.
• In the frame of automata theory, we received one rather interesting result. We have proved functional equivalence of bilateral linear cellular automata arrays and cellular arrays with arbitrary unilateral connection graph. The considered problem is building a cellular automaton, such that an array from automata of this type with arbitrary unilateral divalent connection graphcan solve the same problem as a bilateral linear cellular automata array. It is presumed that the complexity of the cellular automaton does not depend on the number of the automata in the array and, maybe, depends in some regular way on the rank of the respective graph vertex.

Third theme is connected with the problem of high noise immunity in distributed channels under high-speed data transmission, especially in wireless communication channel. One of a way to solve this problem is the use of generalized approach to signal processing in noise. The generalized approach is the combination of optimal signal processing algorithms when the amplitude-phase-frequency structure of signal is "a priori" known and unknown. It is expected that the use of asynchronous protocols constructed on the base of the generalized approach to signal processing in noise will allow to increase the noise immunity in distributed channels.

Using the top-down education approach, the undergraduate andg raduate school students are involved in all steps of the research. They learned the real style of design in the environment System-Circuit-Process, understood the importance of creating the design methodology for circuit optimization and prepared themselves to work in time of very fast changes in micro-electronics and computer science.