Computer Devices Laboratory
The Computer Devices Laboratory (CDL) focuses on education and research on VLSI technologies, devices, and their related area. The main activities are:
- Physics of Semiconductor Devices, (K. Saito) for the undergraduates
- Electronic Circuits, (Y. Hisada) for the undergraduates
- Introduction to Programming, (Y. Hisada) for the undergraduates
- Principles of VLSI Device and Process Technologies, (K. Saito) for the undergraduates
- ULSI Technologies (K. Saito) for the graduates
The main objectives of the research in CDL are to develop new environments for VLSI design, diagnoses, and manufacturing. These will be intelligent manufacturing of VLSIs including a statistical representation, a physical representation, and an expert system representation of the environments. The objects of representations are not restricted in the devices and physical technologies, but will cover from the manufacturing system modeling to the yield enhancement and reliability of VLSI.
His research backgrounds are physics of semiconductor, process and device technologies of MOSLSI, and Computer Integrated Manufacturing (CIM). His current interest is on CIM. He thinks CIM as the centralized information manufacturing. On this concept, he developed a new Yield Modeling, Topography Simulator, and Factory Modeling based on queuing theory and Petri Net. The resource planning system developed in CDL is using in the actual VLSI facilities.
His interest is a computer simulation of semiconductor crystal growth process. The qualityand yield of LSI is in??uenced by the quality of the semiconductor crystal. He is also interested in biometrics. Now he has been developed measurement and analysis system of a living body signal. This research is related to research of LSI for signal processing and analog circuit and sensor. In addition, this research will become the base of ultimate interface computer and human.
|Referred Proceeding Papers|
|[k-saito-01:2002]||Kazuyuki Saito and Sumika Arima. A Simulation Study on Periodical Priority Dispatching of WIP for Product-mix Fabrication. In The 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2002.|
This paper proposes a new dynamic priority dispatching algorithm for the product-mix of work-in-progress(WIP) at a processing station with multiple machines. The algorithm is used to evaluate dispatching prioritywhen eachquantum starts. The priority is defined considering both the number of WIP and the decreasing rate of WIP in the incoming buffer. When the priority is high, a single sort of WIP is assigned to a machine fo a given period, or quantum. This algorithm, named Pseudo Periodical Priority Dispatching (P3D), P3D was examined through Monte Calro simulation. In a product-mix, a machine must be adjusted when the WIP is changed. The adjustment frequency and the degradation of machine utilization due to the adjustment are discussed. The algorithm is able to achieve fair dispatching both at abottleneck processing step and a non-bottleneck processing step.
|[k-saito-02:2002]||Sumika Arima and Kazuyuki Saito. Study on Service Discipline for a Product-mix Manufacturing. In Proc. 2003 Spring Research Meeting of Operations Research Society of Japan, 2003.|
|[k-saito-03:2002]||Kazuyuki Saito. Resource Planning and Dynamic WIP Control in a Product-mix Manufacturing. In Virtual Manufacturing System Research Group Meeting - RSP Project of Fukushima Prefecture, 2003.|
|[k-saito-04:2002]||Kazuyuki Saito. Exercises on VLSI Device Technologies (2nd Edition). The University of Aizu (Computer Device Laboratory), 2002.|
|[k-saito-05:2002]||Sumika Arima. Ph.D. Dissertation: Performance Analyses of Semiconductor Manufacturing Systems, University of Aizu, 2003.|
|[k-saito-06:2002]||hiro Ishikawa. Graduation Thesis: MOSDevice Simulation with VEGA, University of Aizu, 2003.|
|[k-saito-07:2002]||Hiroaki Iwao. Graduation Thesis: Implementation of Stochastic Event in Firing Behavior of Petri Net, University of Aizu, 2003.|
|[k-saito-08:2002]||Yukihiro Kubo. Graduation Thesis: Graphical Data Output Program of Petri Net Simulation, University of Aizu, 2003.|
|[k-saito-09:2002]||Motoki Sakai. Graduation Thesis: Study of Integer DWT in JPEG2000 to Implement on 'Excalibur', University of Aizu, 2003.|
|[k-saito-10:2002]||Tatsuya Shinohara. Graduation Thesis: VHDL Design of IMDCT for MP3, University of Aizu, 2003.|
|[k-saito-11:2002]||Yoshiaki Tachibana. Graduatin Thesis: Development of a tool which predictes a makespan considering the priority and processing procedure in the product-mix, University of Aizu, 2003.|