Computer Education Laboratory
The Computer Education Laboratory (CEL) welcomed Dr. Kitamichi as an associate processor at the beginning of April in 2002 and he has been cotributing wide area both in education and research. His professional field is formal verification for hardware design, which is one of very important fields in VLSI design and is a powerful technology for our laboratory direction.
The academic area of the laboratory mainly covers computer design methodology. Educational course design for VLSI design, formal verification and reconfigurable computing are the major themes of this lab.
Education: We started an education program of VLSI design based on VDEC (VLSI Design and Education Center) support. VDEC offers various kinds of design tools without license cost and accepts chip fabrication orders in low price. This program was developed as an joint research with Prof. Shima in Computer Architecture Laboratory. Web-based manuals for HDL design, verification, and layout tools were developed.
Research: Various kinds of circuits based on PCA (one of dynamically reconfigurable devices) have been designed and implemented. This research has been developed with NTT. Some of the results were published and presented at conferences.
Prof. Kenichi Kuroda: He joined this university in the fall in 1995. He had been a member of the Computer Device Lab for 5 years and moved to this lab in summer 2000. Before his coming to this university, his research topics were superconductor devices, SAW devices, and X-ray optics. After coming this university, he has been interested in VLSI design technology. Especially, dynamically reconfigurable devices such as PCA (Plastic Cell Architecture) are the current major research target.
Prof. Junji Kitamichi: He received the B.S. and Ph.D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Centor at Osaka University, where he was assistant Professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. His research interests include formal methods for VLSI design, design verification, hardware description language, and dynamical reconfigurable architechtures.
|[kuroken-01:2002]||Y. Okuyama, N. Sretasereekul, H. Saito, T. Nannya, and K. Kuroda. Synthesis of Asynchronous Control Circuits Based on Hierarchical CDFG. IPSJ Journal, 43(5):1225-1234, 2002.|
Asynchronous circuits have the potential to solve the problems related to clock signals of synchronous circuits. However, current CADtools for large 0scaleasynchronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper, we suggest a hierarchical Control/Data Flow Graph (CDFG) for flexible partition of asynchronous circuits. We also show that a Signal Transition Graph (STG) for circuit synthesis can be generated from this structure. This structure represents asynchronous circuits using fine grain nodes. The nodes have the flexibility to be partitioned or to be merged into other nodes. In addition, we show an algorithm for a hierarchical CDFG to generate suitable STG for low-level CAD tools. We have confirmed that this algorithm can partition asynchronous circuits with flexibility and generate more compact circuits.
|Referred Proceeding Papers|
|[kuroken-02:2002]||N. Sretasereekul, Y. Okuyama, H. Saito, M. Imai, K. Kuroda, and T. Nanya. Flexible Partitioning of CDFGs for Compact Asynchronous Controllers. In Proc. of the 2002 International Technical Conf. on Circuits/Systems, Computers, and Communications (ITC-CSCC2002), pages 1724-1727. IEICE-ESS, IEEK, ECTI, Jul. 2002.|
Asynchronous circuits have the potential to solve the problems related to parameter varia-tions such as gate delays in deep sub-micron technolo-gies. However, current CAD tools for large-scale asynchronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper, we suggest a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate controllable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm allows designers to assign the maximum number of signals of partitioned nodes considering optimality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.
|[kuroken-03:2002]||K. Kurata, H. Morita, Y. Okuyama, J. Kitamichi, and K. Kuroda. Implementation of the Neural Network on PCA and its Applications. volume 2002, pages 5-13, 2002.|
This paper describes an implementation method of neural network in PCA. In a PCA neuronmodel, aweight in a mathematical neuronmodel is directly output as an output value. Furthermore, output operation can be simplified by reading out of the route information to target neurons and output values from Output RAM on a PP. This method solves a wiring area problem and enables a neural network flexible to change of a threshold value and joint loads. As examples of applications, the PCA neuron model is applied to the EX-OR function and the N-Queen problem, and implementability and applicability are discussed.
|[kuroken-04:2002]||K. Kurata, H. Morita, J. Kitamichi, and K. Kuroda. Implementation of Neural Network on Plastic Cell Architecture (PCA). In 2002 Tohoku-Section Joint Convention Record of IEIEJ, pages 2A-10. IEIEJ, Aug. 2002.|
|[kuroken-05:2002]||T. Ito, M. Ichikawa, K. Ono, J. Kitamichi, and K. Kuroda. A Reconfigurable and Stream-Oriented Vector Processor for Plastic Cell Architecture. In 2002 Tohoku-Section Joint Convention Record of IEIEJ, pages 2A-9. IEIEJ, Aug. 2002.|
|[kuroken-06:2002]||H. Takahashi, K. Ono, J. Kitamichi, and K. Kuroda. Perl in Noise Generator on Plastic Cell Architecture. In 2002 Tohoku-Section Joint Convention Record of IEIEJ, pages 2A-8. IEIEJ, Aug. 2002.|
|[kuroken-07:2002]||T. Ito, A.Takahashi, H.Yamamoto, K. Obata, J. Kitamiti, and K. Kuroda. Implementation Proposal of the Master-Slave Adaptive Load Distribution Model and the Organization of Copy & Elimination Circuits for PCA. In Proc. of 21th PARTHENON Workshop, volume 2002, pages 19-27, 2002.|
In this paper, the adaptive load distribution model was proposed taking advantage of the feature of dynamically reconfiguration of PCA. In the proposal, this paper adopts the master-slave model that consists of the management unit that measures & distributes loads and the processing unit that operates some instructions. This paper proposes for the function that makes the degree of parallel of processor, and the load distribution is implemented with this function. As two functions are managed separately, the overhead of PE reconstruction can be decreased. First function is the copy and elimination PE circuits, the other is to distribute data.
|[kuroken-08:2002]||H. Morita, K. Kurata, J. Kitamiti, and K. Kuroda. Introduction and Investigation of Maximum Neuron to PCA Neural Networks. volume 2002, pages 45-52, 2002.|
In this paper, we offer a way to solve an overhead of dynamic wiring implementation of PCA Neural Networks by introduction of maximum neuron. This model is made of one module, which corresponds to some neurons grouped together. Using this model, we can reduce the size of circuit scale including the number ofdynamic wiring, and performance of neural networks is better than the former model. In this paper, we introduce how to implement the maximum neuron on PCA and consider the realization and application of the model by simulation of Four-color-Map problem.
|[kuroken-09:2002]||A. Suzuki, J. Kitamichi, and K. Kuroda. Design of Layout Management Supporting Tool for Plastic Cell Architecture. In IEICE General Conference 2003. IEICE, Mar. 2003.|
|[kuroken-10:2002]||M. Shima K.Kuroda, K. Oguri. Studyon dynamically reconfigurable architecture, Fundamental Research (C)(2), Ministry of Education Grant-in-Aid: Scientific Research, Contract No.13650381, 2001-2002.|
|[kuroken-11:2002]||K. Kuroda, 2002. Management Board member, PARTHENON Research Society|
|[kuroken-12:2002]||Kentaro Ono. Master Thesis: Study on Instruction Level Parallel Processor with Dynamical Reconfigurability for PCA, University of Aizu, 2002.|
|[kuroken-13:2002]||Mayumi Ichikawa. Master Thesis: Design of Execution Unit for Instruction-Level Parallel Processor on Plastic Cell Architecture, University of Aizu, 2002.|
|[kuroken-14:2002]||Masashi Shiratori. Master Thesis: Implementation of High SpeedModulo Multiplier Circuits for RSA Encryption, University of Aizu, 2002.|
|[kuroken-15:2002]||Hidekuni Yamamoto. Graduation Thesis: Implementation of Eratosthenes's Sieve Using Autonomously Reconfigurable Devices: PCA, University of Aizu, 2002.|
|[kuroken-16:2002]||Kozue Obata. Graduation Thesis: Design of Arithmetic Function Module Selector Unit for ILP Processor on PCA, University of Aizu, 2002.|
|[kuroken-17:2002]||Hiroyuki Morita. Graduation Thesis: Implementation of Neural Network with Maximum Neurons on PCA, University of Aizu, 2002.|
|[kuroken-18:2002]||Atsushi Suzuki. Graduation Thesis: Development if a Placement and Routing Tools for Dynamically Reconfigurable Devices (PCA), University of Aizu, 2002.|
|[kuroken-19:2002]||Susumu Moro. Graduation Thesis: A Timing Verification Tool for Asynchronous Circuits: Plastic Cell Architecture, University of Aizu, 2002.|
|[kuroken-20:2002]||Kae Suzuki. Graduation Thesis: Hardware Implementation of Semaphore and Task Management Functions in Real-Time Operating Systems, University of Aizu, 2002.|
|[kuroken-21:2002]||Ikko Tanaka. Graduation Thesis: Hardware Implementation of Task Management and Interrupt Functions in Real-Time Operating Systems, University of Aizu, 2002.|