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| Department of Computer Hardware |
| Computer Education Laboratory |
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| Kenichi Kuroda
Professor | Junji Kitamichi
Associate Professor |
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The academic area of the laboratory mainly covers computer design methodology. Educational course design for VLSI design, formal verification and reconfigurable computing are the major themes of this lab.
Education:
We started an education program of VLSI design based on VDEC (VLSI De-sign and Education Center) support. VDEC offers various kinds of design tools without license cost and accepts chip fabrication orders in low price. This program was developed as an joint research with Prof. Shima in Computer Architecture Laboratory. Web-based manuals for HDL design, verification, and layout tools were developed.
Research:
Various kinds of circuits based on PCA (one of dynamically reconfigurable devices) have been designed and implemented. For high productivity, library modules, similar to the standard cell library in the conventional VLSI design technology, have been developed and applied to applications for parallel processors, neural networks, and image compression. The Joint research with NTT has been advancing. Some of the results were published and presented at conferences.
As to the traditional synchronous circuit technology, various applications such as bio-informatics and network security have been surveyed based on VDEC technology environment.
Members of the Computer Education Laboratory
Prof. Kenichi Kuroda:
He joined this university mid 1995. He had been a member of the Computer Device Lab for 5 years and moved to this lab in summer 2000. Before his coming to this university, his research topics were super conductor devices, SAW devices, and X-ray optics. After coming to this university, he has been interested in VLSI design technology. Especially, dynamically reconfigurable devices such as PCA (Plastic Cell Architecture) are the current major research direction.
Prof. Junji Kitamichi:
He received the B.S. and Ph.D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Centor at Osaka University, where he was assistant Professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. His research interests include formal methods for VLSI design, design verification, hardware description language, and dynamical reconfigurable architectures. |
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| Refereed Proceeding Papers |
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| [kitamiti-01:2003] | Toshiyuki Ito, Hiroaki Takahashi, Junji Kitamichi, and Kenichi Kuroda. Master-Slave Adaptive Load Distribution Model o. InPCA”, 16th Workshop on Circuits and System in Karuizawa, pages 177-182, Apr. 2003.
We propose and implement new adaptive load distribution model on PCA(Plastic Cell Architecture).(in Japanese) |
| [kitamiti-02:2003] | Keigo Kurata, Hiroyuki Morita, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kurod. ”Implementation of Neural Networks to Decrease Connection Area on Plastic Cell Architecture. In DA Symposium 2003, 2003.
We propose and evaluate a Neural Netowrk on Plastic Cell Architecture to reduce routing area.(in Japanese) |
| [kuroken-01:2003] | T. Ito, H. Takahashi, J. Kitamichi, and K. Kuroda. Master-Slave Adaptive Load Distribution Model on PCA. In Proc. of the 16th Workshop on Circuits and Systems in Karuizawa, pages 177-182. IEICE, IEEE-CSS, IEEE-SPS, April 2003.
In this paper, an adaptive load distribution model is studied taking advantage of the feature of dynamical reconfigurability of PCA. The model adopts a master-slave system consisting of management units and processing units(PE). The management units distribute loads, and the processing units operate instructions. This method changes the number of PE dynamically in proportion to the load. This paper shows the load distribution model and evaluates size and overhead of implemented this model on PCA-1 ( PCA trial chip). |
| [kuroken-02:2003] | K. Kurata, H. Morita, Y. Okuyama, J. Kitamichi, and K. Kuroda. Implementation of Neural Networks to Decrease Connection Area on Plastic Cell Architecture. In Proc. of Design Automation Symposium 2003 (IPSJ Symp. Series 2003-11), pages 79-84. IPSJ, July 2003.
This paper discusses the implementation of neural networks on Plastic Cell Architecture (PCA): PCA neuron model. It makes routing dynamically, so it can decrease connection area and we can apply it to connective variations of neural networks. PCA neuron model needs not multiplier to output values multiplied by synapse weights. Furthermore, PCA neuron model has each memory to manage output behaviors. The usage of this memory enables parallel and distributed processing effectively. We apply it to N-queen problem and Four-colors-map problem, and evaluate our proposal method. |
| [kuroken-03:2003] | T. Ito, K. Ono, M. Ichikawa, Y. Okuyama, and K. Kuroda. Reconfigurable Instruction-Level Parallel Processor Architecture. In Omondi A. and Editor Sesukhin S., editors, Proc. of the Eighth Asia-Pacific Computer Systems Architecture Conference (ACSAC2003), pages 208-220. Springer (Advances in Computer Systems Architecture LNCS 2823), Sep. 2003.
This paper proposes an instruction-level parallel (ILP) processor with architecture reconfigurability.The processor can employ the optimal architecture to applications without loosing generality.Instruction-level parallelism is achieved by expanding the number of PUs depending on its load. Required features of reconfigurable hardware devices for such processors are discussed and the plas- tic cell architecture (PCA) is chosen as a target device for implementation of the ILP processor. Performance with reconfiguration overhead is measured and evaluated. |
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| [kitamiti-03:2003] | Ikko Tanaka, Hidekuni Yamamoto, Keigo Kurata, Junji Kitamiti, and Kenichi Kuroda. The Proposal and Implementation of Distributed Processing Method using Autonomously Reconfigurability in PCA. In FIT2003, pages 311-312, Sep. 2003.
(in Japanese)
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| [kitamiti-04:2003] | Junji Kitamiti and Kenichi Kuroda. Proposal of Abstract Models for Dynamical Reconfigurable System. In FIT2003, pages 313-314, Sep. 2003.
(in Japanese)
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| [kitamiti-05:2003] | Hiroaki Takahashi, Junji Kitamichi, Satoshi Nishimura, and Kenichi Kuroda. A Design of Hadamard Transform with Dynamically Alterability of Block Size and Parallelism. In Technical Report of IEICE,1st Reconf.System, pages 157-164, Sep. 2003.
(in Japanese)
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| [kitamiti-06:2003] | Hiroaki Takahashi, Junji Kitamichi, and Kenichi Kuroda. Proposal of N-dimensional Fast Hadamard Transform Algorithm and Implementation on Dynamically Reconfigurable Device. In IPSJ SIG Technical Report,2004-SLDM-113, pages 53-58, Jan. 2004.
(in Japanese)
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| [kuroken-04:2003] | S. Moro, J. Kitamichi, and K. Kuroda. A Timing Verification Tool for PCA-PP Circuits. In Proc. of 22nd PARTHENON Workshop, volume 2003, pages 5-12, 2003.
In this paper, we propose and implement a timing verification tool for PCA-PP (Plastic Cell Architecture - Plastic Part) circuits. In this tool, in order to handle delays of circuit elements correctly, the symbolic timing simulation method is used and simulates all timing behavior of the circuits. This tool checks that the behavior satisfies given specifications by comparing them. Using this tool, we can find all errors that are caused by the delay of circuit elements on PCA device. |
| [kuroken-05:2003] | I. Tanaka, H. Yamamoto, K. Kurata, J. Kitamichi, and K. Kuroda. Proposal and Implementation of Distributed Processing Method using Autonomous Reconfigurability in PCA. In Proc. of Forum on Information Techinology (FIT2003), 2003. |
| [kuroken-06:2003] | J. Kitamichi and K. Kuroda. Proposal of Abstract Models for Dynamical Reconfigurable Systems. In Proc. of Forum on Information Technology (FIT2003), 2003. |
| [kuroken-07:2003] | H. Takahashi, J. Kitamichi, S. Nishimura, and K. Kuroda. A Design of Hadamard Transform with Dynamically Alterability of Block Size and Parallelism. In Technical Report of IEICE, volume 2003, pages 157-164, 2003.
We propose a design method of 2-dimensional Hadamard Transform, one of the image orthogonal transform, on dynamically reconfigurable devices. This method has dynamic alterability of block size and parallelism of transform system, and this alterability enables the system to cope with variance of requirements. We implemented this 2-dimensional Hadamard Transform on dynamically reconfigurable device, PCA-1. As the result of implementation and evaluations, the proposal method achieves dynamic alterability of block size and parallelism. This system was possible to transform in higher speed with high parallelism. Also, we implemented this system in order to reconfigure in high speed. |
| [kuroken-08:2003] | K. Suzuki, H. Endo, T. Ito, J. Kitamichi, and K. Kuroda. Design of a Bit-variable Divider on Dynamical Reconfigurable Devices. In Proc. of 23rd PARTHENON Workshop, volume 2003, pages 53-60, 2003.
A bit variable divider with invariant circuit configuration was designed and implemented on a dynamically reconfigurable device, PCA (Plastic Cell Architecture). The non-restoring method is used as a division algorithm and speculative and pipeline processing accelerates the calculation. The modulo register can be eliminated by the use of the FIFO function of communicating paths on PCA. This enables variability of the divider circuit. Required PCA cells for this bit-variable divider are 204, independent on bit lengths of a devisor and a dividend up to 4096-bit length. For every 4096-bit expansion, circuit reconfiguration is kept minimal. Simulation reveals proper operation for the bit length from 16 to 4096. |
| [kuroken-09:2003] | K. Kurata, H. Morita, J.Kitamichi, and K. Kuroda. Proposal of the Implementation Method of The Nondeterministically Renewal Neural Networks for Solving the Combinatorial Optimization Problems on PCA-1. In Proc. of 23rd PARTHENON Workshop, volume 2003, pages 45-52, 2003.
Hopfield neural networks are used to solve the combinatorial optimization problems, and some renewal methods of neurons ’states are proposed: the synchronous type, the sequential type, the semi-synchronous type, the nondeterministic type, and so on. With the synchronous type, all neurons’states are renewed in parallel, so the renewal speed is fast. However, the convergence rate is low. With the sequential type, only one neuron ’s state is renewed, and the convergence rate is high. However, its behavior is sequential, so the renewal speed is slow. The performance of the semi-synchronous type is the middle of above two methods. With the nondeterministic type, all neurons behave in parallel, but it is nondeterministic which neurons ’states are renewed. It enables to keep high renewal speed and to improve the convergence rate, but its performance is not cleared and the method has not been implemented on hardware. In this paper, we propose the method to implement the nondeterministically renewal neural networks on PCA-1, which is an asynchronous device with the dynamic and autonomous reconfiguarability, and evaluate its convergence performance applying for the N-Queens problems by software simulation. |
| [kuroken-10:2003] | H. Takahashi, J. Kitamichi, and K. Kuroda. Proposal of N-dimensional Fast Hadamard Transform Algorithm and Implementation on Dynamically Reconfigurable Device. In IEICE Technical Report, volume VLD2003, pages 53-58, 2003.
We propose architecture of Fast Hadamard Transform (FHT), one of the orthogonal transform for digital signals. Our proposed architecture can reduce parallelism of FHT butterfly to 1/ dynamically. Also, we describe a design method for implementing proposed architecture on dynamically reconfigurable devices. Therefore, our FHT system has dynamical alterability of dimension, number of signals, and parallelism. This alterability enables the system to adapt itself to outside requirements changing. We implemented the architecture on a dynamically reconfigurable device PCA-1 with single parallelism. As the result of implementation and evaluation, our system has achieved higher speed performance than our previous work. |
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| [kitamiti-07:2003] | Junji Kitamichi. JSPS, Grants-in-Aid for Scientific Research, 2002-2003. |
| [kitamiti-08:2003] | Junji Kitamichi. The Okawa Fundation, The Research Grant, 2003-2004. |
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| [kitamiti-09:2003] | Junji Kitamichi, Apr. 2003.
IEEE Member
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| [kitamiti-10:2003] | Junji Kitamichi, Apr. 2003.
IPS Member
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| [kitamiti-11:2003] | Junji Kitamichi, Apr. 2003.
IEICE Member
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| [kuroken-11:2003] | Y. Nakane K. Kuroda T. Shiozawa, Y. Okuyama and T. Ito. Method and Equipment fo Dynamical Instruction Generation, App. NO.2003-156366, June 2003. |
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| [kitamiti-12:2003] | Yasuhiro Yamada. Graduation Thesis:Design and Evaluation of an IP Flooding Detection Circuit on High Speed Networks, University of Aizu, 2003.
Thesis Advisor: Junji Kitamichi
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| [kitamiti-13:2003] | Kenji Asano. Graduation Thesis:Implementation of a Simulation Model for Dynamically Reconfigurable Devices, University of Aizu, 2003.
Thesis Advisor: Junji Kitamichi
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| [kitamiti-14:2003] | Shouko Ishizuka. Graduation Thesis:Implementation of Asynchronous Hierarchical Neural Networks on a Dynamically Reconfigurable Device PCA, University of Aizu, 2003.
Thesis Advisor: Junji Kitamichi
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| [kitamiti-15:2003] | Akiko Sasaki. Graduation Thesis: Study of VLSI Design Flow and Implementation of MP3 Decoder, University of Aizu, 2003.
Thesis Advisor: Junji Kitamichi
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| [kitamiti-16:2003] | Hiroaki Tanba. Graduation Thesis: Design and Evaluation of SYN Flood Detection Circuit with Various Pipeline Stages, University of Aizu, 2003.
Thesis Advisor: Junji Kitamichi
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| [kuroken-12:2003] | Toshiyuki Ito. Master Thesis: Proposal of an Instruction Level Parallel Processor with Variable Parallelism, University of Aizu, 2003.
Thesis Advisor: Kenichi Kuroda
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| [kuroken-13:2003] | Keigo Kurata. Master Thesis: Implementation of Neural Networks for Combinatorial Optimization Problems on Dynamically Reconfigurable Device (PCA), University of Aizu, 2003.
Thesis Advisor: Kenichi Kuroda
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| [kuroken-14:2003] | Hiroaki Takahashi. Master Thesis: Design of Hadamard Trans form Circuits on Dynamically Reconfigurable Devices, University of Aizu, 2003.
Thesis Advisor: Kenichi Kuroda
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| [kuroken-15:2003] | Yousuke Ikehata. Graduation Thesis: Implementation of Combinatorial Circuit Synthesis Tool for Plastic Part on Plastic Cell Architecture, University of Aizu, 2003.
Thesis Advisor: Kenichi Kuroda
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| [kuroken-16:2003] | Tomonori Endo. Graduation Thesis: Design and Implementation of Bit-variable Multiplier on Plastic Cell Architecture, University of Aizu, 2003.
Thesis Advisor: Kenichi Kuroda
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| [kuroken-17:2003] | Tomomi Kamiyama. Graduation Thesis: Framework for Self-Reproductive Application on Plastic Cell Architecture (PCA), University of Aizu, 2003.
Thesis Advisor: Kenichi Kuroda
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| [kuroken-18:2003] | Chizuru Saito. Graduation Thesis: Implementation of Hardware/Software Co-simulation Environment for SFL Using System C, University of Aizu, 2003.
Thesis Advisor: Kenichi Kuroda
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| [kuroken-19:2003] | Junichi Nakajima. Graduation Thesis: A Proposal of Algorithms for Time Restriction Logic with Real Number Variables, University of Aizu, 2003.
Thesis Advisor: Kenichi Kuroda
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| [kuroken-20:2003] | Joint Research with NTT Laboratories.
PCA Library
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