Japanese
Department of Computer Hardware

Computer Organization Laboratory

Robert H. FujiiSatoshi NishimuraWanming Chu
Masatoshi Shima
Professor		Robert H. Fujii
Associate Professor		Satoshi Nishimura
Associate Professor		Wanming Chu
Research Associate
Robert Fujii:
2003-2004 academic year activities
  • Neural Networks:
    1. One of the problems that artificial neural networks face is the processing of asynchronous input spike trains. Spiking neurons which model a type of biological neuronal system can overcome such problems. A new method of decoding input spike sequences according to the inter-arrival times of spikes was proposed. A one-to-one correspondence between an input spike sequence and the neuron spike output time was achieved. A relatively simple circuit is needed to implement the new decoding scheme.
    2. A neural network which can learn temporal patterns incrementally was proposed. The proposed network used: a) gaussian functions to represent various output values; and b)chunking to group similar patterns in order to achieve a compact network. The learning capacity limits were evaluated for the worst case sequences. Learning of sequences can be accomplished using a simple one step algorithm.
  • Autonomous AIBO Robot Soccer: The aim of this project was to have a number of AIBO four legged robots autonomously play a game of soccer. This year's activities focused primarily on basic locomotion, basic kicks, simple image processing for self-localization, simple cooperative action between two AIBO robots, and inter-AIBO communication using a wireless LAN.We participated in two national AIBO challenge competitions and placed third in two events. Work is continuing in the areas of multi-robot cooperative learning which will be used in the upcoming December 2004 AIBO soccer competition.
  • Computer-Aided Music: A music chord assignment computer program was developed. This program performs an analysis of the melody and assigns appropriate accompaniment chords. A commercially available tool (MAX) was used for the program development. Work is continuing in the areas of computer-aided music analysis and custom/special effects computer-aided music sound synthesis.
Satoshi Nishimura:
  • Hardware for realistic image synthesis,
  • Computer architecture for computer graphics,
  • Reconfigurable architecture for multimedia applications, and
  • iRealtime systems for computer music.
Wanming Chu:
  • Parallel Multithreaded Architectures
  • Architectures of interconnection networks

Refereed Journal Papers

[fujii-01:2003]Y. Konishi and R. H. Fujii. Incremental Learning of Temporal Sequences Using State Memory and a Resource Allocating Network. In International Joint Conference on Neural Networks. IEEE, 2004.

A network which can learn temporal patterns incrementally is proposed. The learning capacity limits of the network are analyzed for the worst case sequences. Learning of sequences can be performed using a simple one step algorithm.
[fujii-02:2003]H. H. Aminand R. H. Fujii. Input Arrival TimeDependent Decoding Scheme for a SpikingNeural Network. In 12th European Symposium on Artificial Neural Networks. IEEE, 2004.

A new method of decoding input spikes according to their input arrival times is proposed.Only a limited number of neurons are needed to implement the decoding scheme.
[fujii-03:2003]H. H. Amin and R. H. Fujii. Spike Train Decoding Scheme for a Spiking Neural Network. In International Joint Conference on Neural Networks. IEEE, 2004.

A decoding scheme for uniquely distinguishing spike trains using the spike relative arrival times in a spike train is proposed.
[fujii-04:2003]N. Sutou, T. Nishimura, R. H. Fujii, and R. Oka. Spotting Recognition of Concave and Convex Reference Image with Pixel-Wise Correspondence Using Two-Dimensional Continuous Dynamic Programming. In Technical Report of IEICE. IEICE, 2003.

An extension to previously proposed spotting algorithms is proposed in order to make recognition possible for both convex and/or concave images.
[w-chu-01:2003]Wanming Chu and Yamin Li. An Instruction Cache Architecture for Parallel Execution of Java Threads. In P. Fan and H. Shen, editors, Proceedings of the Fourth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'03), pages 180-187, Chengdu, China., Aug. 2003. IEEE, IEEE Press.

Using a traditional superscalar cache architecture in a horizontal multithreading Java processor results in high cache miss ratio caused by the interference among the threads. This paper investigates amultibank instruction cache architecture for horizontal multithreading Java processor to meet the requirements of the high instruction fetch bandwidth. Our simulation results show that the performance improvements are obtained by the low cache miss ratio and the high instruction fetch bandwidth of the proposed cache architecture. The IPC (instructions per cycle) performance is about 19 when the numbers of slots and banks both are 8, about 5 times better than one bank cache.
[w-chu-02:2003] Yamin Li, Shietung Peng, and Wanming Chu. Fault-Tolerant Cycle Embedding in Dual-Cube with Node Faulty. In P. Fan and H. Shen, editors, Proceedings of the Fourth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'03), pages 71-78, Chengdu, China., Aug. 2003. IEEE, IEEE Press.

A low-degree dual-cube was proposed as an alternative to the hypercubes. A dual-cube DC(m) has m+1 links per node where m is the degree of a cluster (m-cube) andonemore link is used for connecting to anode in another cluster. There are 2m+1 clusters and hence the total number of nodes is 22m+1 in a DC(m). In this paper, by using Gray code, we show that there exists a faulty free cycle containing at least 2m+1 -2f nodes with f ≤ m-1 faulty nodes.

Refereed Proceeding Papers

[nisim-01:2003]Hiroaki Takahashi, Junji Kitamichi, Satoshi Nishimura, and Ken'ichi Kuroda. The design of Hadamard transform circuits with dynamically-reconfigurable block size and parallelism. In Proc. of the IEICE first conference on reconfigurable systems. IEICE, Sep. 2003.

Ph.D and Other Theses

[fujii-05:2003]Kondo Satoshi. Graduation Thesis: Neural Network Based Determination of AIBO Robot's Facing Direction, University of Aizu, 2004.

Thesis Advisor: Fujii, R. H.

[fujii-06:2003]Suda Masaya. Graduation Thesis: Cooperative Action by Four Legged Soccer Playing Robots, University of Aizu, 2004.

Thesis Advisor: Fujii, R. H.

[fujii-07:2003]Ebihara Izumi. Graduation Thesis: Image Cue Based Self Localization, University of Aizu, 2004.

Thesis Advisor: Fujii, R. H.

[fujii-08:2003]Satou Shinsuke. Graduation Thesis: Goal Keeper Strategy for Robocup Soccer, University of Aizu, 2004.

Thesis Advisor: Fujii, R. H.

[fujii-09:2003]Fujita Atsushi. Graduation Thesis: Classification of Images Based on Reduced Image Features, University of Aizu, 2004.

Thesis Advisor: Fujii, R. H.

[fujii-10:2003]Hanaizumi Tomohiro. Graduation Thesis: Computer-Aided Music Accompaniment, University of Aizu, 2004.

Thesis Advisor: Fujii, R. H.

[nisim-02:2003]Hayato Sugahara. Graduation Thesis: Evaluation and Implementation of Texture Compression Hardware, University of Aizu, 2003.

Thesis Advisor: Satoshi Nishimura

[nisim-03:2003]Yoshiaki Nakaya. Graduation Thesis: Evaluation of Accuracy and Speed for the Partially Solving Method, University of Aizu, 2003.

Thesis Advisor: Satoshi Nishimura

[nisim-04:2003]Akiko Takahashi. Graduation Thesis: Parallel Processing of the Partially Solving Method, University of Aizu, 2003.

Thesis Advisor: Satoshi Nishimura