Computer Organization Laboratory

Tosiaki Miyazaki Professor	Satoshi Nishimura Associate Professor	Hiroshi Saito Assistant Professor

The following researches are progressed in Computer Organization Laboratory: Toshiaki Miyazaki: has mainly two topics as follows: Die-hard sensor network is a wireless sensor network that has an autonomous function alternation mechanism among sensor nodes as well as ordinary wireless sensor network capabilities such as automatic network establishment. With this mechanism, we can realized self-organized and maintenance-free sensor network systems. Its applications include surveillance of disaster-hit region, and river and forest monitoring. We are developing not only sensor node hardware but also protocols equipped to the sensor node. Custom Computing is a research field to realize a dedicated hardware using programmable logic devices such as FPGAs (Field Programmable Gate Arrays) in order to solve a give problem effectively. We focused on two applications; motif search and 3D-DCT. Motif search accelerator: It is very important to detect a common motif, i.e., partial base sequence, from DNA sequences in bioinformatics research field, and some methods have been proposed. Gibbs sampling is one of the popular methods to perform it. To accelerate Gibbs sampling with a dedicated hardware, we reconsidered the way of the evaluation-value calculation part that is the performance bottleneck of Gibbs sampling, and realized a motif search accelerator on an FPGA. Array processor for 3D-DCT: Collaborated with the Distributed Parallel Processing Laboratory in the University of Aizu, a 3D array processor for 3D-DCT was designed. In addition, the prototype system was implemented using FPGAs to evaluate the feasibility of the architecture. Satoshi Nishimura: Hardware for realistic image synthesis, Computer architecture for computer graphics, Reconfigurable hardware for multimedia applications, and Realtime systems for computer music Hiroshi Saito: Our research interests are design of asynchronous circuits and its automation. Asynchronous circuits are circuits where circuit components are controlled by pairs of local handshake signals instead of a global clock signal. Because of the absence of a global clock signal, asynchronous circuits are low power and low electromagnetic interference compared to synchronous counter parts which use global clock signals. Our research topics are as follows. Synthesis of asynchronous circuits from a behavioral model specified by C language Design of low power and low electromagnetic interference asynchronous circuits Synthesis of network-on-chip architecture from a behavioral model

Refereed Proceeding Papers

[hiroshis-01:2008]	N. Hamada, Y. Shiga, H. Saito, T. Yoneda, C. Myers, and T. Nanya. A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation (Tool Paper). In International Conference on Application of Concurrency to System Design, pages 50–55, June 2008.
	This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation.
[miyazaki-01:2008]	S. Sedukhin, T. Miyazaki, and K. Kuroda. 3-D Toroidal Array Processor for Multidimensional DSP Transforms. In N.A., editor, Proc. The second International Conference on 3D System Integration (3D-SIC2008), pages 401–410, National Institute of Informatics, May 2008. ASET, 3D-SIC.
	We present the forward and inverse 3-D separable transforms in the form of chained matrix-matrix multiply-add and transposition operations. Then, a new orbital systolic-like implementation of the 3-D transforms and its inverse on a 3-D toroidal array processor are proposed. In this implementation, a required transposition is avoided, but each 1-D transform becomes data dependent from other coexisting 1-D transforms. The main difference of our orbital implementation is in dimensionality of I/O: we design an array processor under assumption when all 3-D data is immediately available for the fine-grain massively-parallel computing and during processing we do not destroy an integrity (space-time locality) of processed data.
[miyazaki-02:2008]	T. Miyazaki, Y. Nomoto, Y. Sato, and S. Sedukhin. Array Processor Featuring an Effective FIFO-based Data Stream Management. In Proc. IEEE 8th International Conference on Computer and Information Technology (CIT2008), pages 255–260, July 2008.
	In array processors, data I/O management is the key to realizing high-speed matrix operations that are often required in signal and image processing. In this paper, we propose an array processor utilizing an effective data I/O mechanism featuring external FIFOs. The FIFOs are used to buffer initial matrix data and partially processed results. Therefore, if all required data are stored in the FIFOs, matrix operations, including the algorithm to solve the Algebraic Path Problem (APP), can be performed without any data I/Os. In addition, we can eliminate register files from the processing elements (PEs) if we construct the PE array by controlling the external FIFOs systematically and transferring the data from (to) the FIFOs to (from) the PE array. This enables us to simplify each PE structure and realize a large array processor with limited hardware resources. Here, the FIFOs themselves can be easily realized using conventional discrete FIFO or memory chips.
[miyazaki-03:2008]	H. Fukuhara, K. Kawauchi, I. Koseda, R. Fujita, T. Miyazaki, S. Saito, A. Kara, and T. Hayashi. Integration of Sensor Networks with Information Systems using the Messaging Network. In Proc. SICE Annual Conference 2008 (SICE 2008), August 2008.
	This paper describes an approach to integrate sensor networks with information systems using the so-called messaging network architecture. A messaging network is an overlay network with a rich set of message handling capabilities. The use of messaging network reduces the complexity and the maintenance burden of the integrated sensor information systems. Message mediation enables not only interoperation of various applications but also integration of a diversity of data set to produce useful information. The proposed approach naturally leads to an SOA-based sensor network design. The decomposition of a system into services has many advantages in developing secure scalable multi-tenant information systems. The requirements on a messaging network for sensor network systems are presented.
[miyazaki-04:2008]	T. Miyazaki, R. Kawano, Y. Endo, and D. Shitara. Sensor Network for Surveillance of Disaster-hit Region. In Proc.IEEE International Symposium on Wireless and Pervasive Computing (ISWPC2009), pages 1–6, Feb. 2009.
	We propose a new type of wireless sensor network system named die-hard sensor network. Conceptually, this system performs continuous monitoring without any maintenance, even if some sensor nodes die. A significant difference between our system and the ordinary wireless sensor networks is that each sensor node in our system should have an automatic sensing-function alternation mechanism in addition to the conventional communication protocols for wireless sensor networks. Owing to the mechanism, our system is suitable for mission-critical applications; this is because many sensor nodes often die due to frequent changes in the environment. In this paper, after introducing the concept of the die-hard sensor network, we present a prototype system that is dedicated to the surveillance of disaster-hit regions.

Unrefereed Papers

[hiroshis-02:2008]
	N. Hamada, Y. Shiga, T. Konishi, and H. Saito. A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. In DA symposium 2008, pages 259–264, 2008.
[hiroshis-03:2008]
	Y. Kunisawa and H. Saito. A Delay AdjustmentMethod for FPGA Implementation of Asynchronous Circuits with Bundled-data Implementation. In DA symposium 2008, pages 253–258, 2008.
[miyazaki-05:2008]
	D. Shitara and T.Miyazaki. Function Alternation Algorithm inWireless Sensor Network. In IPSJ 2008 4th IPSJ Tohoku-section Workshop, Feb. 2009.
[miyazaki-06:2008]
	R. Kawano and T. Miyazaki. An effective data I/O mechanism utilizing FIFOs for an array processor. In The Society of Instrument and Control Engineers (SICE), The 18th Intelligent System Symposium (FAN2008), Oct. 2008.
[miyazaki-07:2008]
	R. Kawano and T. Miyazaki. Dual optimization method for dynamic sensor allocation and effective data aggregation in wireless sensor networks. In IPSJ 71th general conference, volume 2U-2, March 2009.
[miyazaki-08:2008]
	M. Kinugawa, K. Kawauchi, T. Miyazaki, S. Saito, and T. Hayashi. Construction Method of Sensor Networks using the Message Network Architecture. In IPSJ SIG Report, volume 2008-DPS-135, June 2008.
[miyazaki-09:2008]
	Y. Sato, J. Tazawa, and T. Miyazaki. An FPGA implementation of Gibbs sampling method towards high-speed motif search. In IEICE Tecnical Report, volume RECONF2008-88, Jan. 2008.
[miyazaki-10:2008]
	D. Shitara and T. Miyazaki. Function Modification Method for Multiple Sensor Nodes using Over-The-Air-Programming. In IEICE, volume B- 20-9, Sept. 2008.
[miyazaki-11:2008]
	Y. Sato, J. Tazawa, and T. Miyazaki. Ａ high-speed circuit for motif detection. In IPSJ 71th general conference, volume 6ZD-6, March 2009.
[miyazaki-12:2008]
	Y. Ikegaki, T. Miyazaki, and S. Sedukhin. An Array Processor Performing 3D-DCT Effectively. In IPSJ 71th general conference, volume 2U-2, March 2009.

Grants

[hiroshis-04:2008]	H. Saito. Ministry of Education Scientific Research Fund, 2006-2008.
[hiroshis-05:2008]	T. Yoneda, M. Imai, A. Matsumoto, and H. Saito. Core Research for Evolutional Science and Technology of Japan Science and Technology Corporation, 2008-2013.
[miyazaki-13:2008]	T. Miyazaki. Grant from JST ’Seeds Hakkutsu Shiken’, 2008.
[miyazaki-14:2008]	T. Miyazaki. JSPS Grant-in-Aid for Scientific Research (No. 18500060), 2006-2008.

Academic Activities

[hiroshis-06:2008]	H Saito, 2008. Councilor, IPSJ Tohoku Branch
[hiroshis-07:2008]	H Saito, 2008. Associate Editor, IPSJ Transactions on System LSI Design Methodology
[hiroshis-08:2008]	H Saito, Oct. 2008. OTechnical Program Committee, IEEE International Symposium on Asynchronous Circuits and Systems
[miyazaki-15:2008]	T. Miyazaki, 2008. Steering committee member, Technical Group for Reconfigurable Systems
[miyazaki-16:2008]	T. Miyazaki, 2008. Technical Program Committee Member, RC education 2007 (International Workshop on Reconfigurable Computing Education)
[miyazaki-17:2008]	T. Miyazaki, 2008. Area Chairs, CIT2008 (8th International Conference on Computer and Information Technology)
[miyazaki-18:2008]	T. Miyazaki, 2008. Technical Program Committee Member, UUWSN2008 (The International Workshop on Ubiquitous UnderWater Sensor Network 2008)
[miyazaki-19:2008]	T. Miyazaki, 2008. Reviewer
[miyazaki-20:2008]	T. Miyazaki, 2008. Reviewer, The IEICE Transactions
[miyazaki-21:2008]	T. Miyazaki, 1984 – present. Member
[miyazaki-22:2008]	T. Miyazaki, 1988 – present. Member
[miyazaki-23:2008]	T. Miyazaki, 1986 – present. Member
[miyazaki-24:2008]	T. Miyazaki, 2008. Technical Program Committee Member, COOLChips (IEEE Symposium on Low- Power and High-Speed Chips)
[miyazaki-25:2008]	T. Miyazaki, 2008. Technical Program Committee Member, ISVLSI2008 (IEEE International Symposium on VLSI)

Patents

[miyazaki-26:2008]	S. Sedukhin, T. Miyazaki, and K. Kuroda. Array Processor 2008- 119884, May 2008.
[miyazaki-27:2008]	T. Miyazaki. Sensor Equipment, Sensing Information Aggregation System, Sensing Function AlternationMethod, and Software Program for Sensing Function Alternation 2008-230593, Sept. 2008.

Ph.D, Master and Bachelor Theses

[hiroshis-09:2008]	Yuuki Shiga. Master Thesis: Bit-width Optimization for Asynchronous Circuits with Bundled-data Implementation, University of Aizu, 2008. Thesis Advisor: Saito, H.
[hiroshis-10:2008]	Takao Konishi. Master Thesis: Pipeline Synthesis for Asynchronous Circuits with Bundled-data Implementation, University of Aizu, 2008. Thesis Advisor: Saito, H.
[hiroshis-11:2008]	Kazuya Enko. Graduation Thesis: A Floorplan Method for Asynchronous Circuits with Bundled-data Implementation, University of Aizu, 2008. Thesis Advisor: Saito, H.
[hiroshis-12:2008]	Ryo Ouchi. Graduation Thesis: A Comparison of Energy Consumption between Synchronous Circuit and Asynchronous Circuit, University of Aizu., 2008. Thesis Advisor: Saito, H.
[miyazaki-28:2008]	Yuka Sato. Master Thesis: High-speed motif searching circuit and its FPGA implementation, University of Aizu, 2008. Thesis Advisor: T. Miyazaki
[miyazaki-29:2008]	Naoto Takeishi. Graduation Thesis: I/O Architecture for a 3-D Array Processor and its Implementation, University of Aizu, 2008. Thesis Advisor: T. Miyazaki
[miyazaki-30:2008]	Yuuki Tanno. Graduation Thesis: A Negotiation-based Multi-sink Data Transfer Protocol for Wireless Sensor Networks, University of Aizu, 2007. Thesis Advisor: T. Miyazaki
[miyazaki-31:2008]	Ryouhei Kawano. Master Thesis: Graph coloring-based optimization for dynamic sensor allocation and effective data aggregation in wireless sensor networks, University of Aizu, 2008. Thesis Advisor: T. Miyazaki
[miyazaki-32:2008]	Hidenori Igari. Graduation Thesis: Multihop Data Forwarding in Wireless Sensor Networks, University of Aizu, 2008. Thesis Advisor: T. Miyazaki
[miyazaki-33:2008]	Yuki Ikegaki. Graduation Thesis: An Array Processor Performing 3D-DCT Effectively, University of Aizu, 2008. Thesis Advisor: T. Miyazaki
[nisim-01:2008]	Kyogo Yokota. Master Thesis: Multi-resolution Analysis of Musical Expressions, University of Aizu, 2009. Thesis Advisor: Satoshi Nishimura
[nisim-02:2008]	Masaaki Yoshizawa. Graduation Thesis: Real-Time Musical Score Tracking System Using a Performance Position Analysis Algorithm, University of Aizu, 2009. Thesis Advisor: Satoshi Nishimura
[nisim-03:2008]	Akiko Kumanaka. Graduation Thesis: Speed-up of Ray-Tracing with Bounding Volume Thesis Advisor: Satoshi Nishimura
[nisim-04:2008]	Yoshiaki Hagane. Graduation Thesis: Handling 3D Sound Diffraction in FDM Using GPU for Speed-up, University of Aizu, 2009. Thesis Advisor: Satoshi Nishimura

Others

[miyazaki-34:2008]	T. Miyazaki. VLecture, ’Functional Safety of Software’, JASA, Aug./29/2008
[miyazaki-35:2008]	T. Miyazaki. Invited Talk, ’Die-hard Sensor Network: Its Concept and Applications’, IEEE CIT2008, July 2008
[miyazaki-36:2008]	T. Miyazaki. Lecture, ’Introduction to Reconfigurable Computing’, Toyama Prefectural University, Dec./12/2008

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