Adaptive Systems Laboratory

Kenichi Kuroda Professor	Junji Kitamichi Associate Professor	Yuichi Okuyama Assistant Professor	Ben A. Abderazek Assistant Professor

The name of the laboratory changed from ”Computer Education Lab.” to ”Adaptive Systems Lab.” in 2008. The academic area of this laboratory mainly covers computer design methodology. Reconfigurable computing, formal verification, network on a chip, and educational course design for VLSI are the major themes of this lab. Education: We have been developing an education program of VLSI design based on VDEC (VLSI Design and Education Center) support. VDEC offers various kinds of design tools without license costs and accepts chip fabrication orders in low price. This program was started as a joint research with Prof. Shima, who left from this university in 2004, in Computer Architecture Laboratory in 2001. Web-based manuals for HDL design, verification, and layout tools have been developed and are being updated depending on VDEC support tools every year. Collaborating with Computer Organization Lab. and Logic Circuit Design Lab., we are establishing educational materials on embedded systems and FPGA-based design courseware. We welcomed Prof. Ben A. Abderazek in 2007, and now, members of our laboratory are four professors, 8 master program students, and 14(B4)+13(B3) graduate thesis students. Research: Recently, we are now focusing on the higher level design circumstances, such as UML, SystemC, and other HDLs. We developed a new design flow from SFL (one of the HDLs) to SystemC for improving the design efficiency. As to the VDEC-based synchronous circuit technology, various applications such as bio-informatics and network security have been surveyed. We started a new approach to high performance computing systems with reconfigurable devices collaborating with the RIKEN research group, the PROGRAPE Project. The target of this project is“ Desktop Supercomputing System ”. “ Desktop ”means low-cost with commercially available FPGAs and PCs. We have been developing interface circuits and new applications such as fluid dynamics, data mining, and others. In collaboration with Prof. S. Sedukhin (Distr. Parallel Proc. Lab.), we have been developing a prototype of RapidMarix Processor System, which is a kind of torus array system specified for high performance matrix operation. We also started a new approach to high performance computer architecture, ”Queue Processor” based on Prof. Ben’s research background. Members of the Computer Education Laboratory Prof. Kenichi Kuroda: Before his coming to this university, he belonged to the NTT laboratories and he was engaged with the research on superconductor devices, SAW devices, and X-ray optics. He joined this university mid 1995. He received his Dr. Eng. from Tokyo University in 1991. He had been a member of the Computer Device Lab for 5 years and moved to this lab in summer 2000. After coming to this university, he was interested in VLSI design technology. Especially, dynamically reconfigurable devices such as PCA (Plastic Cell Architecture) are the current major research direction. Prof. Junji Kitamichi: He received the B.S. and Ph. D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Centor at Osaka University, where he was assistant Professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. His research interests include formal methods for VLSI design, design verification, hardware description language, dynamical reconfigurable architechtures, and real-time systems. Prof. Abderazek Ben Abdallah: He received his BTS degree from Sfax University in 1990. The BE, ME degrees from HUST Univ. in 1994 and 1997 respectively. In 2002, he received his Ph.D. degree from the Univ. of Electro-communications. From 2002 to 2007, he was a research associate at the Univ. of Electro-communications, Graduate School of Information Systems, then Assistant Professor at the network computing laboratory. He joined the Univ. of Aizu in 2007. His research interests span the areas of computer architecture, embedded systems, and VLSI. Prof. Yuichi Okuyama: He was born in 1975. He received the M. S and Ph. D degrees in computer science and engneering from the University of Aizu in 1999 and 2002, respectively. He entered NTT Network Innovation Laboratories and was engaged with the development of PCA (Plastic Cell Architecture) devices. He joined the University of Aizu in 2005 as an assistant professor. His crrent interests are implementation of applications and tools for disign automation on reconfigurable device(FPGA and other devices) and design of hardware for scientific calculations. Students : Master Program M2:Fumiko Ohori, Daisuke Ohwada, Kenji Mitome. M1:Shuhei Igari, Mizuho Shiga, Hiroki Hoshino, Taichi Maekawa, Masashi Masuda. Graduation Thesis Students: B4:Yukihiro Yoshida, Kazunori Nemoto, Shoichi Igarashi, Yasue Nagumo, Haruka Niinuma, Yasushi Haga, Reo Honjoya, Shohei Miura, Tsubasa Murohashi, Kenichi Mori, Ryuhei Morita, Yoshitomo Yabuki, Yuka Yasuda. B3:Takahiro Honma, Kei Ito, Takahiro Uesaka, shunnichi Kato, Tetsuya Kishinami, Yumiko Kimezawa, Yukihiro Kotani, shouta Niki, Yuki Sakuma, Kazuhiro Maeda, Shuta Yamamoto, Yoshuke Wakisaka, Mitsuhiro Watanabe.

Refereed Journal Papers

[benab-01:2009]	A. Canedo, A. Ben Abdallah, and M. Sowa. Compiler Support for Code Size Reduction using a Queue-based Processor. Transactions on High- Performance Embedded Architectures and Compilers, 2, Issue 4(4):269–285, – 2009.
	Queue computing delivers an attractive alternative for embedded systems. The main features of a queue-based processor are a dense instruction set, high-parallelism capabilities, and low hardware complexity. This paper presents the design of a code generation algorithm implemented in the queue compiler infrastructure to achieve high code density by using a queue-based instruction set processor. We present the efficiency of our code generation technique by comparing the code size and extracted parallelism for a set of embedded applications against a set of conventional embedded processors. The compiled code is, in average, 12.03more compact than MIPS16 code, and 45.1addition, we show that the queue compiler, without optimizations, can deliver about 1.16 times more parallelism than fully optimized code for a register machine.
[benab-02:2009]	A. Canedo, A. Ben Abdallah, and M. Sowa. Efficient Compilation for Queue Size Constrained Queue Processors. The Journal of Parallel Computing, 35(–):213–225, – 2009.
	Queue computers use a FIFO data structure for data processing. The essential characteristics of a queue-based architecture excel at satisfying the demands of embedded systems, including: compact instruction set, simple hardware logic, high parallelism, and low power consumption. The size of the queue is an important concern in the design of a realizable embedded queue processor. We introduce the relationship between parallelism, length of data dependency edges in data flow graphs and the queue utilization requirements. This paper presents a technique developed to make the compiler aware of the size of the queue register file and, thus, optimize the programs to effectively utilize the available hardware. The compiler examines the data flow graph of the programs and partitions it into clusters whenever it exceeds the queue limits of the target architecture. The presented algorithm deals with the two factors that affect the utilization of the queue, namely: parallelism and the length of variables’ reaching definitions. We analyze how the quality of the generated code is affected for SPEC CINT95 benchmark programs and different queue size configurations. Our results show that for reasonable queue sizes the compiler generates code that is comparable to the code generated for infinite resources in terms of instruction count, static execution time, and instruction level parallelism.
[kuroken-01:2009]	S. Sedukhin, T. Miyazaki, and K. Kuroda. Orbital Systolic Algorithms and Array Processors for Solution of the Algebraic Path Problem. IEICE TRANS. INF. & SYST., E93-D(3):534–541, 2010.
	The algebraic path problem (APP) is a generalframework which unifies several solution procedures for a number of well-known matrix and graph problems. In this paper, we present a new 3-dimensional (3-D) orbital algebraic path algorithm and corresponding 2-D toroidal array processors which solve the n x n APP in the theoretically minimal number of 3n time-steps. The coordinated time-space scheduling of the computing and data movement in this 3-D algorithm is based on the modular function which preserves the main technological advantages of systolic processing: simplicity, regularity, locality of communications, pipelining, etc. Our design of the 2-D systolic array processors is based on a classical 3-D -¿2-D space transformation. We have also shown how a data manipulation (copying and alignment) can be effectively implemented in these array processors in a massively-parallel fashion by using a matrix-matrix multiply-add operation.

Refereed Proceeding Papers

[benab-03:2009]	S. Miura, A. Ben Abdallah, and K. Kuroda. PNoC - Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration. In FAN2009, editor, The 19th Intelligent System Symposium (FAN 2009), volume – of –, pages 314–317, –, September 2009. –, FAN 2009.
	Current Multicore Systems-On-Chip (MCSoC) execute applications that need highly parallel processing. Networks-On-Chip (NoC) largely alleviate the limitations of busbased solutions. NoCs can have regular or ad hoc topologies, and functional validation is essential to estimate their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. With our emulation approach, designers can explore a various range of solutions, as well as quickly characterize performance figures.
[benab-04:2009]	Y. Haga, A. Ben Abdallah, and K. Kuroda. Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECGEKG Processing. In Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for The 19th Intelligent System Symposium (FAN 2009), volume – of –, pages 298–303, –, Sept. 2009. FAN 2009, –.
	Electrocardiography (ECG/EKG) is an interpretation of the electrical activity of the heart over time captured and externally recorded by electrodes. It is an essential practice in heart medicine, which faces computational challenges, especially with 12 lead signals or more. This paper exploits parallel processing techniques to process electrocardiography computation kernels in parallel and under different sampling frequencies. This work is part of a project named BANSMOM projecta. We present a novel Period-Peak Detection (PPD) algorithm for heart signals processing via the use of a novel embedded MCSoC architecture. The ECG/EKG algorithm and the system architecture are presented in a fair amount of details.
[benab-05:2009]	Abderazek Ben Abdallah Masashi Masuda, Arquimedes Canedo. Software and Hardware Design Issues for Low Complexity High Performance Embedded Processor. In 38th International Conference on Parallel Processing Workshops, pages 558–565. IEEE, Sept. 2009.
	Queue processor offers an attractive option in the design of general purpose and applications specific systems. This paper presents software and hardware design issues for extracting high instruction level parallelism for the 32-bit QueueCore processor.We propose code generation algorithm for the QueueCore architecture. Compiling for the QueueCore requires a new approach since the concept of registers disappears. The compiler extracts more parallelism than the optimizing compiler for a RISC machine over a set of various numerical benchmark programs. In addition, we are able to generate in average about 23RISC processors.
[benab-06:2009]	K. Mori, A. Ben Abdallah, and K. Kuroda. Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA. In The 19th Intelligent System Symposium (FAN 2009), pages 318–321. FAN 2009, September 2009.
	QCurrent Systems-On-Chip (SoCs) execute applications which demand extensive parallel processing. Networks-On-Chip (NoCs) provide a good way of realizing efficient interconnections, and largely alleviate the limitations of bus-based solutions. In this paper, we present architecture and preliminary design result of a complexity effective on-chip interconnection network, named OASIS, on FPGA. The NoC was designed and prototyped with respect to simplicity and a small hardware footprint.
[benab-07:2009]	Abderazek Ben Abdallah Masashi Masuda, Arquimedes Canedo. Efficient Code Generation Algorithm for Natural Instruction Level Parallelismaware Queue Architecture. In The 19th Intelligent System Symposium (FAN 2009), pages pp.308–313. FAN 2009, September 2009.
	Best Presentation Award. Queue based instruction set architecture processor offers an attractive option in the design of embedded systems. In our previous work, we proposed a novel queue processor architecture as a starting point for hardware/software design space exploration for embedded applications. In this paper, we present a high performance 32-bit QueueCore architecture. This work presents novel code generation algorithm for the QueueCore architecture. Compiling for the QueueCore requires a new approach since the concept of registers disappears. The compiler extracts more parallelism than the optimizing compiler for a RISC machine over a set of various numerical benchmark programs. In addition, we are able to generate in average about 23RISC processors.
[kitamiti-01:2009, kuroken-02:2009]	Kenichi Kuroda Yasue Nagumo, Junji Kitamichi. Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Devices. In Proceeding of 18th IP-Embedded Systems Conference(IP - ESC 2009),pages 42–45. IEEK, Dec. 2009.
	Recently, multi-core processors have been featured in embedded field. Especially, with regard to reconfigurable devices, several system constructions can be implemented easily. The Real-Time OS(RTOS) for a multi-core processor has many limitations for system constructions on the reconfigurable devices. Therefore, it is very important to verify that the system construction satisfies the limitations for RTOS and that the primitive system calls operate properly. In addition, when these devices are used in the system development such as task design, the consumption of hardware/software resources, and the performance evaluation of primitive system calls on the reconfigurable devices are very important. In this paper, we propose several inter-processor communication mechanisms for two multi-core processors on an FPGA as the primitive operations for the system tasks and evaluate them. We adopted NIOS II processor as the embedded processors and the TOPPERS/ FMP kernel as the operating system for multi-core processor.
[kitamiti-02:2009]	Junji Kitamichi. Proposal of Instruction Level Modeling for Dynamically Reconfigurable Processor using SystemC. In Proceeding of 17th IFIP/IEEE International Conference On Very Large Scale Integration(VLSISOC 2009), page 03, Oct. 2009.
	Recently, various kinds of Dynamically Reconfigurable Processors (DRPs) have been proposed. In this paper, we describe a modeling method of a DRP using a Dynamic Module Library (DML), which we have developed for the modeling of generalpurpose dynamically reconfigurable architectures at the system design level. The DML is an extended SystemC library and enables the modeling of the dynamic generation and elimination of modules, ports and channels and the dynamic connection and dispatch between port and channel. Using the DML, we can model the DRP naturally at the abstract level, where the instruction set architecture and the structure specification of DRP are decided. The proposed processor consists of a core part, dynamically reconfigurable operation units and a controller for them, and we describe the modeling method of them.
[kitamiti-03:2009]	Takuji Hieda Taichiro Imamura Junji Kitamichi Yoshinori Takeuchi Keishi Sakanushi, Junya Okamoto and Masaharu Imai. Electronic Triage System for Disaster Medical Treatment. In Proceeding of Embedded Systems Symposium2009 (ESS 2009), pages 147–152, Oct 2009.
	To transport a lot of injured persons to the medical institution in a short time, the triage is useful in the disaster scene where many casualties occur at the same time. The current triage is operated with the paper triage tag. Since the ”paper triage tag” does not show current conditions of injured persons, injured persons whose conditions change suddenly may be missed out. This paper proposes a electronic triage system that measure vital signs of a injured person and show the condition of the injured person. Experimental results show that the condition of the injured person in 15m away can be easily checked visually.
[kitamiti-04:2009, kuroken-03:2009, okuyama-01:2009]	F. Ohori, Y. Okuyama, J. Kitamichi, K. Kuroda, and T. Hamada. Evaluation of Image Filtering using Particle Interaction Accelerator on FPGA. In Proc. of the 24th Int. Tech. Conf. on Circuits/Systems Computors and Communications (ITC-CSCC 2009), pages 42–45. IEEK, July, 2009.
	Specific purpose processors are available as an accelerated calculation framework that is less expensive than supercomputers and can be used for scientific calculations and development of leading-edge technologies. These processors are assisting various issues because of these inexpensive advanced hardware technologies. This paper focuses on this advantage and presents image filter processing with one of the specific purpose processors. Image filter processing calculation is proceeded with one of specific purpose processors, PROGRAPE-4 that is specialized in particle calculations. We demonstrate the effective utilization by considering image filter processing as inter-particle calculations.

Unrefereed Papers

[kitamiti-05:2009]	Kazunori Nemoto and Junji Kitamichi. A Refinement of Neural Network Algorithm for Channel Assignment Problem Using Parallel Execution. In Proceedings of the 2010 IEICE General Conference,, pages DS–1–2, March 2010.
[[kuroken-04:2009]	S. MIURA, A. Ben A., and K. KURODA. Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration. In Proc. of the 34th Parthenon Wokshop, pages 105–108. NGO PARTHENON Org., Sep. 2009.
	Current Multicore Systems-On-Chip (MCSoC) execute applications that need highly parallel processing. Networks-On-Chip (NoC) largely alleviate the limitations of busbased solutions. NoCs can have regular or ad hoc topologies, and functional validation is essential to estimate their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to 　explore, evaluate and compare a wide range of NoC solutions with a very limited effort. With our emulation approach, designers can explore a various range of solutions, as well as quickly characterize performance figures.
[kuroken-05:2009]	S. Miura, A. Ben Abdallah, and K. Kuroda. PNoC - Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration. In Proc. of the 19th Intelligent System Symposium (FAN2009) and the 1st Int. Workshop on Aware Computing (IWAC2009), pages A4–2. JSFTII, Sep. 2009.
	Current Multicore Systems-On-Chip (MCSoC) execute applications that need highly parallel processing. Networks-On-Chip (NoC) largely alleviate the limitations of busbased solutions. NoCs can have regular or ad hoc topologies, and functional validation is essential to estimate their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. With our emulation approach, designers can explore a various range of solutions, as well as quickly characterize performance figures.
[kuroken-06:2009]	K. Mori, A. Ben Abdallah, and K. Kuroda. Design and Evaluation of a Complexity Effective Network-on-ChipArchitecture on FPGA. In Proc. of the 19th Intelligent System Symposium (FAN2009) and the 1st Int. Workshop on Aware Computing (IWAC2009), pages A4–3. JSFTII, Sep. 2009.
	Current Systems-On-Chip (SoCs) execute applications which demand extensive parallel processing. Networks-On-Chip (NoCs) provide a good way of realizing efficient interconnections, and largely alleviate the limitations of bus-based solutions. In this paper, we present architecture and preliminary design result of a complexity effective on-chip interconnection network, named OASIS, on FPGA. The NoC was designed and prototyped with respect to simplicity and a small hardware footprint.
[kuroken-07:2009]	Y. Haga and K. Kuroda A. Ben Abdallah. Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing. In Proc. of the 19th Intelligent System Symposium (FAN2009) and the 1st Int. Workshop on Aware Computing (IWAC2009), pages F3–2. JSFTII, Sep. 2009.
	Electrocardiography (ECG/EKG) is an interpretation of the electrical activity of the heart over time captured and externally recorded by electrodes. It is an essential practice in heart medicine, which faces computational challenges, especially with 12 lead signals or more. This paper exploits parallel processing techniques to process electrocardiography computation kernels in parallel and under different sampling frequencies. This work is part of a project named BANSMOM projecta. We present a novel Period-Peak Detection (PPD) algorithm for heart signals processing via the use of a novel embedded MCSoC architecture. The ECG/EKG algorithm and the system architecture are presented in a fair amount of details.

Grants

[benab-08:2009]	Ben Abdallah Abderazek. Smart Body Area Network System for Mobility Monitoring, 2009. BANSMOM Project
[kitamiti-06:2009]	Junji Kitamichi. The Telecommunications Advancement Foundation, 2009-2010.

Academic Activities

[benab-09:2009]	Ben Abdallah Abderazek, 2009. IEEE Member
[benab-10:2008]	Ben Abdallah Abderazek, 2009 Steering committee chair of 4th International Symposium on Embedded Multicore Systems-on-chip (MCSoC-09), Vienna, Austria, 2009. Publication co-chair of the 4th International Conference on Frontier of Computer Science and Technology (FCST2009), Shanghai, China, 2009. Program co-chair of IEEE International Conference on Embedded Software and Systems, Hangzhou, Zhejiang, China, 2009. IPC member of The 19th Intelligent System Symposium（FAN 2009）, Aizu-Wakamatsu, Japan, 2009. IPC member of IEEE 8th International Conferences on Embedded Computing, Dalian, China, 2009.
[kitamiti-07:2009]	J. Kitamichi, 2007. Member, IEICE
[kitamiti-08:2009]	J. Kitamichi, 2007. Member, IEEE
[kitamiti-09:2009]	J. Kitamichi, 2007. Member, IPSJ
[kuroken-08:2009]	Kenichi Kuroda, 2009. Member of IEICE Student Activity Support Committee
[kuroken-09:2009]	Kenichi Kuroda, 2009. IEICE Regular member
[kuroken-10:2009]	Kenichi Kuroda, 2009. Member of Management Board of PARTHENON Society (NPO)
[kuroken-11:2009]	Kenichi Kuroda, 2009. IPSJ Regular member
[kuroken-12:2009]	Kenichi Kuroda, 2009. JSAP Regular member
[okuyama-02:2009]	Yuichi Okuyama, 2009. IPSJ Regular member
[okuyama-03:2009]	Yuichi Okuyama, 2009. Committee of PARTHENON Society (NPO)
[okuyama-04:2009]	Yuichi Okuyama, 2009. IEICE Regular member

Ph.D, Master and Graduation Theses

[benab-11:2009]	Mori Kenichi. Graduation Thesis: OASIS Network-on-Chip, Univ. of Aizu, MArch 2010. Thesis Advisor: Abderazek Ben Abdllah
[benab-12:2009]	Yuuki Omoto. Graduation Thesis: QSoC, University of Aizu, March 2010. Thesis Advisor: Abderazek Ben Abdllah
[benab-13:2009]	Reo Honjoya. Graduation Thesis: Assembler, UNiv. of Aizu, March 2010. Thesis Advisor: Abderazek Ben Abdllah
[benab-14:2009]	Haga Yasuyoshi. Graduation Thesis: BANSMOM Project, Univ. of Aizu, March 2010. Thesis Advisor: Abderazek Ben Abdllah
[benab-15:2009]	Miura shohei. Graduation Thesis: Parameterizable Network-on-Chip, UNiv. of Aizu, March 2010. Thesis Advisor: Abderazek Ben Abdllah
[kuroken-13:2009]	Fumiko Ohori. Master Thesis: Precision Improvement of Short-Range Forces in SPH Simulation on Standard Floating Point Processing, University of Aizu, 2009. Thesis Advisor: Kenichi Kuroda
[kuroken-14:2009]	Ryuhei Morita. Graduation Thesis: Development of a Flexible PROGRAPE System on SoC-based FPGA, University of Aizu, 2009. Thesis Advisor: Kenichi Kuroda
[kuroken-15:2009]	Shoichi Igarashi. Graduation Thesis: Task Scheduling for an Accelerator FPGA Board, University of Aizu, 2009. Thesis Advisor: Kenichi Kuroda
[kuroken-16:2009]	Daisuke Ohwada. Master Thesis: A Cycle-accurate Simulator Visualizing Behaviors of MIPS Processors, University of Aizu, 2009. Thesis Advisor: Kenichi Kuroda
[kuroken-17:2009]	Kenji Mitome. Master Thesis: Implementation of Micro Instructions and API for a Torus Type Matrix Processor, University of Aizu, 2009. Thesis Advisor: Kenichi Kuroda
[okuyama-05:2009]	Haruka Niinuma. Graduation Thesis: Proposal of an Auomatic Classification Method in Pulse Diagnosis Using Self-Organizing Maps, University of Aizu, 2009. Thesis Advisor: Yuichi Okuyama
[okuyama-06:2009]	Yuka Yasuda. Graduation Thesis: Acceleration of Two-Dimensional SPH Computation on a Multi-core Processor, University of Aizu, 2009. Thesis Advisor: Yuichi Okuyama
[okuyama-07:2009]	Tsubasa Murohashi. Graduation Thesis: Comparison of Algorithms for N-Queen Problem using Functional Program Language, University of Aizu, 2009. Thesis Advisor: Yuichi Okuyama
[okuyama-08:2009]	Yukihiro Yoshida. Graduation Thesis: Acceleration of 2D Continuous Dynamic Programming by Memory Reduction and Parallelization, University of Aizu, 2009. Thesis Advisor: Yuichi Okuyama

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