Kenichi Kuroda
Professor
Junji Kitamichi
Associate Professor
Yuichi Okuyama
Assistant Professor
Ben Abdallah Abderazek
Assistant Professor
|
Kenichi Kuroda Professor |
Junji Kitamichi Associate Professor |
Yuichi Okuyama Assistant Professor |
Ben Abdallah Abderazek Assistant Professor |
The academic area of this laboratory mainly covers computer design methodology. Reconfigurable computing, formal verification, network on a chip, and educational course design for VLSI are the major themes of this lab.
Short history of the Lab.:
"Computer Education Lab." started in 1993.
1993-1998 Prof. A. Taubin 2000- Prof. K. Kuroda
2002- Prof. J. Kitamichi joined.
2005- Prof. Y. Okuyama joined.
2007- Prof. A. Ben joined.
2008- The title of the laboratory changed to "Adaptive Systems Lab.".
Members of our laboratory are four professors, 11 master program students, and 10(B4)+11(B3) graduate thesis students. In the 1st semester, a student joined as a short stay student from Rose-Hulman Inst. Tech. in US.
Education:
We have been developing an education program of VLSI design based on VDEC (VLSI Design and Education Center) support. VDEC offers various kinds of design tools without license costs and accepts chip fabrication orders in low price. This program was started as a joint research with Prof. Shima, who left from this university in 2004, in Computer Architecture Laboratory in 2001. Web-based manuals for HDL design, verification, and layout tools have been developed and are being updated depending on VDEC support tools every year. Colaborating with Computer Organization Lab. and Logic Circuit Design Lab., we are establishing educational materials on embedded systems and FPGA-based design courseware.
Research: Recently, we are now focusing on the higher level design circumstances, such as UML, SystemC, and other HDLs. We developed a new design flow from SFL (one of the HDLs) to SystemC for improving the design efficiency. As to the VDEC-based synchronous circuit technology, various applications such as bio-informatics and network security have been surveyed.
We started a new approach to high performance computing systems with reconfigurable devices collaborating with the RIKEN research group, the PROGRAPE Project.
The target of this project is "Desktop Supercomputing System". "Desktop" means low-cost with commercially available FPGAs and PCs. We have been developing interface circuits and new applications such as fluid dynamics, data mining, and others. In collaboration with Prof. S. Sedukhin (Distr. Parallel Proc. Lab.), we have been developing a prototype of RapidMarix Processor System, which is a kind of torus array system specified for high performance matrix operation.
We also started a new approach to high performance computer architecture, "Queue Processor" and Network-on-Chip Architecure based on Prof. Ben's research background.
Members of the Computer Education Laboratory
Prof. Kenichi Kuroda:
Before his coming to this university, he belonged to the NTT laboratories and he was engaged with the research on superconductor devices, SAW devices, and X-ray optics. He joined this university mid 1995. He received his Dr. Eng. from Tokyo University in 1991. After coming to this university, he had been a member of the Computer Device Lab. for 5 years and moved to Computer Education lab. in summer 2000. he was interested in VLSI design technology. Especially, reconfigurable device systems are the current major research direction.
Prof. Junji Kitamichi:
He received the B.S. and Ph.D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Centor at Osaka University, where he was assistant professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. From 2008, he joined the research project "Advanced Wireless Communication Technology for Efficient Rescue Operations" in JST(Japan Science and Technology Agency). His research interests include formal methods for VLSI design, design verification, hardware description language, dynamical reconfigurable systems, and real-time systems.
Prof. Abderazek Ben Abdallah:
He received his BTS degree from Sfax University in 1990. The BE, ME degrees from HUST Univ. in 1994 and 1997 respectively. In 2002, he received his Ph.D. degree from the Univ. of Electro-communications. From 2002 to 2007, he was a research associate at the Univ. of Electro-communications, Graduate School of Information Systems, then Assistant Professor at the network computing laboratory. He joined the Univ. of Aizu in 2007. His research interests span the areas of computer systems, embedded systems, and VLSI.
Prof. Yuichi Okuyama:
He was born in 1975. He received the M.S and Ph.D degrees in computer science and engneering from the University of Aizu in 1999 and 2002, respectively. He entered NTT Network Innovation Laboratories and was engaged with the development of PCA (Plastic Cell Architecture) devices. He joined the University of Aizu in 2005 as an assistant professor. His current interests are implementation of applications on hardware, tool development for design automation on reconfigurable device(FPGA and other devices) and design of hardware for scientific calculations.
Students :
Master Program:
M2:Shuhei Igari, Mizuho Shiga, Hiroki Hoshino, Taichi Maekawa, Masashi Masuda. M1:Yukihiro Yoshida, Shoichi Igarashi, Shohei Miura, Kenichi Mori, Ryuhei Morita, Akram Ben Ahmed. Short Stay: Adam Esch (Rose-Hulman Inst. Tech.)
Graduation Thesis Students:
B4:Kei Ito, Takahiro Uesaka, shunichi Kato, Yumiko Kimezawa, Yukihiro Kotani, shota Niki, Kazuhiro Maeda, Shuta Yamamoto, Yoshuke Wakisaka, Mitsuhiro Watanabe.
B3:Tomotaka Kasahara, Ryosuke Kaji, Ryuya Okada, Kazuji Kobayashi, Yoshiaki Kondo, Toshihiro sato, Yuji Nishimaki, Taichi Hasegawa, Yoshuke Haraguchi.
A. Ben Abdallah, M. Masuda, A. Canedo, and K. Kuroda. Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture. The Journal of Super Computing, pages DOI: 10.1007/s11227 010-0409-z, 2011.
This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computation-based processor. The instructions of a queue processor implicitly read and write their operands making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new effcient code generation algorithm for the QueueCore. For a set of numerical benchmark programs our compiler extracts more parallelism than the optimizing compiler for a RISC machine by a factor of 1.38. Through the use of QueueCore's reduced instruction set, we are able to generate 20% and 26% denser code than two embedded RISC processors.
Kenechi Mori, A. Esch, A. Ben Abdallah, and K. Kuroda. Advanced Design Issues for OASIS Network-on-Chip Architecture. In IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications, pages 74-79, 2010.
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a solution to problems exhibited by the shared bus communication approach in System-On-Chip (SoC) implementations including lack of scalability, clock skew, lack of support for concurrent communication and power consumption. The communication requirement of this paradigm is affected by architecture parameters such as topology, routing, buffer size etc. In this paper, we propose advanced optimization techniques for OASIS NoC, a NoC we previously designed.We describe the architecture and the novel optimization techniques in details. Hardware complexity and preliminary performance results are also given
A. Ben Abdallah. Efficient Parallel ECG Processing Algorithm Toward the Design of Flexible Health Monitoring System for Elderly People. In Innovation Research Journal, pages 24-27, March 2010.
The advance in multicore systems pave the way for the development of single-chip solutions for computationally intensive bio-medical applications with potential health benefits for human beings. Electrocardiography (ECG) is an interpretation of the electrical activity of the heart over time captured and externally recorded by electrodes. An effective approach to speed up this and other biomedical operations is to integrate a very high number of processing elements in a single chip so that the massive scale of fine-grain parallelism inherent in several bio-medical applications can be exploited efficiently. The research reports efforts in the design of a novel health monitoring system based on multicore system and a new Period-Peak-Detection (PPD) algorithm. The proposed system exploits parallel processing techniques to process ECG computation kernels in parallel and over high sampling rate acquisition.
Akram Ben Ahmed, A. Ben Abdallah, and K. Kuroda. Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC. In EEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications, pages 24-27, Nov. 2010.
(This paper got Best Paper Award) During this last decade, Network-on-Chips (NoC) have been proposed as a promising solution for future systems on chip design. It offers more scalability than the sharedbus based interconnection, allows more processors to operate concurrently. Because NoC has dedicated wires, performance can be predicted. In this context, we proposed a 2D-NoC named OASIS, which is a 4x4 mesh topology design using Wormhole switching and Stall-and-Go flow control scheme. Although OASIS-NoC has its advantages over the shared-bus based systems, it has also some limitations such as high power consumption, high cost communication, and low throughput. To overcome those limitations we propose a 3D-NoC (3D OASIS-NoC) which is an extension to our 2D OASIS-NoC. In this paper we describe the 3D OASIS-NoC architecture in a fair amount of detail and present preliminary evaluation results.
A. Ben Abdallah, Y. Haga, and K. Kuroda. An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records. In IEEE Proc. of the 39th he International Conference on Parallel Processing Workshops, pages 99-103, September 2010.
Electrocardiography (ECG) is an interpretation of the electrical activity of the heart over time captured and externally recorded by electrodes. An effective approach to speed up this and other biomedical operations is to integrate a very high number of processing elements in a single chip so that the massive scale of fine-grain parallelism inherent in several biomedical applications can be exploited efficiently. In this paper, we exploit parallel processing techniques to process electrocardiography computation kernels in parallel. We present an efficient ECG analysis algorithm based on Period-Peak Detection (PPD) approach. The system is implemented in a multicore System-on-Chip. System architecture and evaluation results are given in detail.
Kazunori Nemoto and Junji Kitamichi. Improvement of Accuracy and Processing Speed of a Maximum Neural Network Algorithm for a Channel Assignment Problem. In 2010 International Symposium on Nonlinear Theory and its Applications (NOLTA2010), pages pp.127-130, 2010.
In recent years,the popularity of cellular mobile communication systems increases steady. However, the usable frequency spectrum or channels for the Cellular Radio Networks(CRNs) are limited. Thus, algorithms for an efficient utilization of channels: the Channel Assignment Problem(CAP) have become important. In this paper, we propose an improved Neural Network Algorithm (NNA) with parallelism to improve solution accuracy and speed-up processing for the static CAP in CRNs. Our proposed algorithm achieves the improved solution accuracy because of large hill-climbing. In addition, parallel processing using multi-thread can achieve faster processing. We verify performance through simulations using benchmark problems and our proposed algorithm can search better solutions and obtains faster processing speeds than the existing one.
Yukihiro Yoshida, Koushi Yamaguchi, Yuichi Yaguchi, Yuichi Okuyama, Ken ichi Kuroda, and Ryuichi Oka. Accelerate Two-Dimensinal Continuous Dynamic Programming by Memory Reduction and Parallel Peocessing. In Proc. of IADIS International Conf. on Applied Computing (AC 2010), pages 61-68. IADIS, Oct. 2010.
This paper contains a proposal for optimizing and accelerating the computation of two-dimensional continuous dynamic programming (2DCDP). 2DCDP processing is optimized by memory reduction and parallelization using OpenMP. We apply buffer resizing and utilize toggle-type buffers to reduce the required memory size. In addition, same-rank processes and pixel correspondence calculation are parallelized by OpenMP instructions to reduce the computation cost/time of 2DCDP. For accumulation, we also apply a realignment of buffering addresses for SIMD on multi-cores/multi-processors. The experimental results show that the computational time and the memory usage have reduced to about 1/4 and 1/5 of the original ones, respectively. Moreover, the concurrency of 2DCDP hot-spot is improved from 5.8 to 7.1 on a quadcore CPU with 8 threads.
Mizuho Shiga and Junji Kitamichi. System Design Level Simulation Environment of Multi-core Processor NiosII. In Proceedings of the 73rd National Convention of IPSJ, pages pp.1-89-90, 2011.
Syuhei Igari, Junji Kitamichi, Yuichi Okuyama, and Kenichi Kuroda. Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator. In IEICE Techical Report, vol. 110, no. 362, RECONF2010-77, pages pp. 163-168, 2011.
Kazuaki Takahashi, Yuichi Yaguchi, Koushi Yamaguchi, Yukihiro Yoshida, Yuichi Okuyama, and Ryuichi Oka. Realization of Free View-point TV using Two-dimensional Continuous Dynamic Programming. In Meeting on Image Recognition & Understanging (MIRU2010), July 2010.
A. Ben Abdallah. Multicore Systems-On-Chip: Practical Hardware/Software Design Issues. ISBN 978-90-78677-22-2. World Scientific Publishers, 2010.
Preface: Conventional on-chip communication design mostly use ad-hoc approaches that fail to meet the challenges posed by the next-generation MultiCore Systems-onChip (MCSoC) designs. These major challenges include wiring delay, predictability, diverse interconnection architectures, and power dissipation. A Network-on-Chip (NoC) paradigm is emerging as the solution for the problems of interconnecting dozens of cores into a single system-on-chip. However, there are many problems associated with the design of such systems. These problems arise from non-scalable global wire delays, failure to achieve global synchronization, and difficulties associated with non-scalable bus-based functional interconnects. The book consists of three parts, with each part being subdivided into four chapters. The first part deals with design and methodology issues. The architectures used in conventional methods of MCSoCs design and custom multiprocessor architectures are not flexible enough to meet the requirements of different application domains and not scalable enough to meet different computation needs and different complexities of various applications. Several chapters of the first part will emphasize on the design techniques and methodologies. The second part cov ers the most critical part of MCSoCs design xxx the interconnections. One approach to addressing the design methodologies is to adopt the so-called reusability feature to boost design productivity. In the past years, the primitive design units evolved from transistors to gates, finite state machines, and processor cores. The network-on-chip paradigm offers this attractive property for the future and will be able to close the productivity gap. The last part of this book delves into MCSoCs validations and op timizations. A more qualitative approach of system validation is based on the use of formal techniques for hardware design. The main advantage of formal methods is the possibility to prove the validity of essential design requirements. As formal languages have a mathematical foundation, it is possible to formally extract and verify these desired properties of the complete abstract state space. Online testing techniques for identifying faults that can lead to system failure are also surveyed. Emphasis is given to analytical redundancy-based techniques that have been developed for fault detection and isolation in the automatic control area.
Ben Abdallah Abderazek, 2010.
I served as: (1) Session chair, 39th International Conference on Parallel Processing, San Diego, Sept. 13-16, 2010. (2) Steering committee chair, 5th International Symposium on Embedded Multicore Systems-on-chip (MCSoC-10), San Diego, Sept. 13-16, 2010. (3) Area Chair of Distributed Algorithms and Systems track , 5th Int. Conf. on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Fukuoka, Nov. 4-6, 2010. (4) Area Chair of Parallel and Distributed Algorithms track of the 13th Int. Conf. on Network-Based Information Systems, Takayama, Sep. 1416, 2010. (5) PC member of IEEE Symposium on Low-power and High-Speed Chips, Tokohama, April 20-22, 2011.
J. Kitamichi, 2010.
Member. IEEE
J. Kitamichi, 2010.
Member, IPSJ
J. Kitamichi, 2010.
Member, IEICE
Kenichi Kuroda, 2010.
IPSJ Regular member
Kenichi Kuroda, 2010.
JSAP Regular member
Kenichi Kuroda, 2010.
Member of Management Board of PARTHENON Society (NPO)
Kenichi Kuroda, 2010.
IEICE Regular member
Kenichi Kuroda, 2010.
Member of IEICE Student Activity Support Committee
Y. Okuyama, April 2010.
Commettee member, PARTHENON Society (NPO)
Y. Okuyama, April 2010.
Regular member, Japan Society for Software Science and Technology
Y. Okuyama, April 2010.
Regular member, IEICE
Y. Okuyama, April 2010.
Regular member, IPSJ
Shunichi Kato. Graduation Thesis: Shared Memory MultiQueueCore Processor Design, School of Computer Science and Engineering, March 2011.
Thesis Adviser: Ben Abdallah Abderazek
Taichi Maekawa. Master Thesis: Design and Evaluation of DualMode Processor Architecture, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: Ben Abdallah Abderazek
Yumiko Kimezawa. Graduation Thesis: Multicore SoC Architecture for Realtime Data Intensive ECG Processing, School of Computer Science and Engineering, March 2011.
Thesis Adviser: Ben Abdallah Abderazek
Masashi Masuda. Master Thesis: Produced Order Queue Compiler Design, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: Ben Abdallah Abderazek
Takahiro Uesaka. Graduation Thesis: OASIS NoC Topology Optimization with ShortPath Link, School of Computer Science and Engineering, March 2011.
Thesis Adviser: Ben Abdallah Abderazek
Hiroki Hoshino. Master Thesis: Development of Parallel Queue Processor Architecture and its Integrated Development Environment, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: Ben Abdallah Abderazek
Kazuhiro Maeda. Graduation Thesis: Precision Improvement in SPH Simulation Using Computational Grid, School of Computer Science and Engineering, March 2011.
Thesis Adviser: Y. Okuyama
Shota Niki. Graduation Thesis: GPGPU Acceleration of Smoothed Particle Hydrodynamics Simulation, School of Computer Science and Engineering, March 2011.
Thesis Adviser: Y. Okuyama
2011 THE UNIVERSITY OF AIZU ALL RIGHTS RESERVED