Annual Review 2010 > Division of Computer Engineering

Computer Devices Laboratory

Kazuyuki Saito


Yasuhiro Hisada

Assistant Professor

The Computer Device Laboratory (CDL) focuses on education and research on VLSI technologies, devices, and their related area.


For the undergraduate students;

Physics of Semiconductor Devices (K. Saito)

Principles of VLSI Devices and Process Technologies (K. Saito)

Japanese Writing (K. Saito)

Information and Industries (K. Saito)

Introduction to Programming (Y. Hisada)

Programming C (Y. Hisada)

Advanced Electronics (Y. Hisada)

For the graduate students

ULSI Technologies (K. Saito)


The main objectives of the research in CDL are to develop new environment for VLSI design, diagnoses, and manufacturing. These will be an intelligent manufacturing of VLSIs including a statistical representation, a physical representation, and an expert system representation of the environments. The objects of representations are not restricted in the devices and physical technologies, but will cover from the manufacturing system modeling to the yield enhancement and reliability of VLSI. Currently, a new system to estimate resources for the semiconductor manufacturing has developed. The system has been used in the semiconductor companies for monthly planning of their human and machinery resources. In addition a novel dispatching algorithm for the mixed LSI production is developed. The mixed production is inevitable in the system LSI fabrication. The new dispatching algorithm, named pseudo periodical priority dispatching, is superior to FCFS in setup frequency, and in response time, and to SPT in tardiness. Therefore, the algorithm will be promising to reduce the cost in the future semiconductor manufacturing.

Research Projects have been performed in CDL are as follows:

  1. Research on the Product-mix VLSI Manufacturing (Grant-In-Aid for Scientific Research)

  2. Low Power VLSI Technologies

  3. New Dispatching Method for VLSI Manufacturing

  4. Manufacturing System Modeling and Simulation Tool based on Petri Net

  5. Optimization of Resources for VLSI Production (with Fujitsu Tohoku Electro nics)

  6. Wavelet Analyses on the Electrocardiogram (with Fukushima Medical University)

  7. A new Approach for Logic Design (with Fujitsu Tohoku Electronics)

  8. Cooperative Co-evolutionally Hardware and its Application (Grant-In-Aid for Scientific Research)

  9. Research on Parameter Extraction for VLSI Simulation (with NTT Laboratories)

  10. Research on Defect Analysis of the Implanted Silicon Layer (with NTT Laboratories)

Ph.D., Master and Graduation Theses


Shiho Iwagami. Graduation Thesis: eliability Evaluation for Sleep Stage Estimation Method, University of Aizu, 2010.

Thesis Adviser: Y. Hisada