Tsuneo Tsukahara
Professor
Robert H. Fujii
Associate Professor
Yukihide Kohira
Assistant Professor
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Tsuneo Tsukahara Professor |
Robert H. Fujii Associate Professor |
Yukihide Kohira Assistant Professor |
Tsuneo Tsukahara:
Software-Defined Radio Transceivers
Related to this topic, the following work was done in 2010.
A High-Precision Quadrature Modulator and a Spectrum-Analyzing Method for Multi-band Wireless Transceivers:
Recently the demand for wireless systems such as sensor networks has been rapidly growing. However, radio-wave resources are limited and invaluable especially in these days. Therefore, software-defied radios (SDRs) and cognitive radios, which is a principal application of SDR, can be the key to greatly improving frequencyspectrum efficiency. SDRs demand flexibility and reconfigurability in RF (Radio Frequency) circuits. Therefore, a spectrum-efficient wireless transceiver architecture is indispensable. In this research, we proposed a multi-band wireless transceiver using a high-precision complex quadrature modulator and a spectrumanalyzing receiver suitable for sensor networks. As the final goal after 2-to-3 year research, we would like to establish a "reconfigurable wireless communicator," whose frequency band can be changed according to communication conditions and/or a country's regulations using reconfigurable RF and baseband processors and downloadable software. This is a kind of cognitive radios based on SDR (Software-Defined Radios). In the 2010, we have concentrated on circuit design of the high-precision complex quadrature modulator (QMOD) in the transmitter. In recent years, multi-level modulations such as Quadrature Amplitude Modulation (QAM) are or will be used in Wireless LANs, digital TVs, and the 4th-generation cell-phones. So, very small modulation errors of QMOD are strongly demanded. RF/IF building blocks we designed have three features as follows:
A high-precision complex quadrature modulator is newly devised, which features local-oscillator (LO) phase and amplitude error compensation in the complex-signal domain.
We applied windowed integration sampler (WIS) to the IF Fourier transform integration. The WIS also shows filtering with the sinc function.
Low-distortion and wideband techniques are devised for RF low-noise amplifiers and mixers.
Yukihide Kohira:
Design Automation Methodology for LSI Circuits
Due to the increase of scales of LSI circuits and the decrease of time to market of LSI products, LSI designers use design automation systems in order to design LSI circuits. Since the performance of LSI product depends heavily on the used design automation systems, the importance of researching design automation has increased.
Our research interests are design automation methodology in general-synchronous framework, deskew, and routing method for PCB design.
General-synchronous Framework In the conventional clock synchronous framework which is adopted in most circuits, a clock is distributed to all registers periodically and simultaneously. In this framework, many issues have been pointed out. On the other hand, in general-synchronous framework, a clock is distributed periodically to all registers but the clock is not necessarily distributed simultaneously. General-synchronous framework is expected to give essential solutions for the issues in the conventional clock synchronous framework with low introduction costs since circuits can be improved by modifying only clock circuits to satisfy clock schedules in which circuits work correctly. The target of our research is to establish a design automation system which can design LSI circuits in general-synchronous framework which satisfy with required circuit performance ash as high frequency, low power, and so on.
Deskew In resent LSI chips, process variations increase significantly because of the progress of the process technology. The process variations significantly cause delay variations such as gate delay variations or wire delay variations, and delay variations affect the performance and the yield of VLSI chips. The countermeasure to reduction of the yield ratio and the redesign, chips are designed so that the designed circuit has margins. These margins are realized by using fast modules with large size and high power consumption. We investigated deskew technique to reduce margins. Deskew is the adjustment of the programmable delay elements after the fabrication of LSI chips. If the circuit cannot work at the testing process after the fabrication of LSI chips, the circuit can be recovered by deskew technique.
PCB routing Due to the increase of operation frequency, signal propagation delay is requested to achieve a specification with very high accuracy. In PCB routing, the signal propagation delay of the net is controlled by controlling its wire length. We investigate routing methods which obtain routes whose target lengths are realized with high accuracy in single-layer. The goal of our research is to establish a routing methodology which can be applied to any PCB routing problems such as multi-layer, multi-terminal, and so on.
Y. Kohira and A. Takahashi. CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles. IEICE Trans. Fundamentals, E93-A(12):2380-2388, 2010.
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve specifications with very high accuracy. In order to achieve the severe requirements, signal propagation delay is taken into account in the routing design of PCB (Printed Circuit Board). In the routing design of PCB, the controllability of wire length is often focused on since it enables us to control the routing delay. In this paper, we propose CAFE router which obtains routes of multiple nets with target wire lengths for single layer routing grid with obstacles. CAFE router extends the route of each net from a terminal to the other terminal greedily so that the wire length of the net approaches its target wire length. Experiments show that CAFE router obtains the routes of nets with small length error in short time.
K. Shinoda, Y. Kohira, and A. Takahashi. Single-Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing. In 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2010), pages 278-283, October 2010.
In recent Printed Circuit Boards (PCB), the design size and density have increased, and the improvement of routing tools for PCB is required. Although there are several routing tools that generate high-quality global routings when only horizontal and vertical segments are used, PCB designers are not satisfied with these tools because high-density PCBs require segments that have arbitrary directions. In this paper, we propose a routing method that maintains the advantages of tools that use horizontal and vertical segments only, while handling higher density designs by using 45-degree segments to locally relax the routing density.
T. Tsukahara, T. Tsushima, and H. Ito. Evolution of Transceiver Architectures toward Software-Defined and Cognitive Radios (Invited Paper). In 2010 Int'l Conference on Solid State Devices and Materials (SSDM), pages pp. 99-100, 2010.
The history of RF transceiver architectures is discussed, touching on new circuit technologies such as complex quadrature modulators. Finally, recent technology trends of RF circuits for Software-Defined and Cognitive Radios are overviewed.
T. Tsukahara, H. Ito, and T. Tsushima. Evolution of Low-Power CMOS RF Transceivers (Invited Paper). In 2010 Asia-Pacific Radio Science Conference (AP-RSAC), pages CBDFK1, 2010.
The history of CMOS RF circuits is discussed, touching on new low-IF receivers using complex filtering. Finally, recent technology trends of low-power CMOS RF circuits are overviewed.
Y. Kohira and A. Takahashi. [Invited Talk] Length-Matching Routing on Single Layer for PCB Routing Design. In IEICE Technical Report (VLD2010-47), volume 110, pages 31-36, September 2010.
K. Shinoda, Y. Kohira, and A. Takahashi. A Congested Area Specification for Single Layer Printed Circuit Board Routing. In IEICE Society Conference, volume A, page 66, September 2010.
K. Shinoda, Y. Kohira, and A. Takahashi. An Efficient Congested Area Specification and Congestion Relaxation by 45 Degree Line for Single Layer Printed Circuit Board Routing. In IEICE Technical Report (VLD2010-9), volume 110, pages 79-84, May 2010.
Y. Kohira and A. Takahashi. An Evaluation of Clock Tree Based on Clustering in General-Synchronous Framework. In IEICE Society Conference, volume A, page 63, September 2010.
T. Tsushima and T. Tsukahara. Design of a High-Precision Complex Quadrature Modulator. In The Papers of Technical Meeting on Electronic Circuits, IEE Japan, 2010.
T. Tsushima and T. Tsukahara. A High-Precision Complex Quadrature Modulator. In The 2010 IEICE Society Conference, 2010.
T. Tsukahara. Commissioned Research Fund from ADVANTEST Corporation, 2010.
Y. Kohira, April 2010.
Program Committee Member, 23rd Workshop on Circuits and Systems in Karuizawa, IEICE
T. Tsukahara, 2010.
Member of the IEICE Electronics Society Technical Committee on Integrated Circuits and Devices
T. Tsukahara. Complex Quadrature Modulator and Demodulator, and Applicable Quadrature Mixers, July 2010.
Taiki Konno. Graduation Thsisi: Achieving accurate robotic arm control using a physics-based simulator, School of Computer Science and Engineering, March 2011.
Thesis Adviser: R. Fujii
Hitoshi Haga. Graduation Thesis: Person identification based on handwritten hiragana, School of Computer Science and Engineering, March 2011.
Thesis Adviser: R. Fujii
Takashi Ishizaka. Master Thesis: An Opampless Amplifier Suitable for High-Speed Pipeline ADCs, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Tsukahara
Satoru Hanzawa. Graduation Thesis: Design of Second-Order AntiAliasing Windowed-Integration Samplers, School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Tsukahara
Yuya Maeda. Graduation Thesis: A Study of Stacked-FET Power Amplifiers in Standard CMOS Technology, School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Tsukahara
Kazuto Hirata. Graduation Thesis: Noise Canceling Techniques for Low-Noise Amplifiers, School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Tsukahara
Hideyuki Ito. Master Thesis: An Integration Sampler with Embedded Higher-Order FIR Filtering for SDR Receivers, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Tsukahara
T. Tsukahara. Seminar: Basics and Applications of CMOS Analog RF Circuit Design. J-TECHNO INC, Aug. 2010.
T. Tsukahara. Seminar: Design of CMOS RF Circuits. Technological Media Center, Sept. 2010.
T. Tsukahara. History and Future Trends of CMOS RF-IC Research and Development -Expectations for Young Researchers. Lecture for Graduate School of Osaka Univ., June 2010.
T. Tsukahara. Seminar: History and Future Trends of CMOS RF-IC Research and Development. Advanced Analog Technology Seminar (Osaka Univ.), Oct. 2010.
T. Tsukahara. Seminar: IT Wireless Communication Technologies. Aizu Monozukuri Gijuku, Jan. 2011.
T. Tsukahara. CMOS RF Integrated Circuits -Overview and Perspective. Special Open Lectures on 'Beyond CMOS' (Univ. of Aizu), April 2010.
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