Annual Review 2010 > Division of Computer Engineering

Computer Logical Design Laboratory

Tsuneo Tsukahara

Professor

Robert H. Fujii

Associate Professor

Yukihide Kohira

Assistant Professor

Tsuneo Tsukahara:

Yukihide Kohira:

Refereed Journal Papers

[kohira-01:2010]

Y. Kohira and A. Takahashi. CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles. IEICE Trans. Fundamentals, E93-A(12):2380-2388, 2010.

Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve specifications with very high accuracy. In order to achieve the severe requirements, signal propagation delay is taken into account in the routing design of PCB (Printed Circuit Board). In the routing design of PCB, the controllability of wire length is often focused on since it enables us to control the routing delay. In this paper, we propose CAFE router which obtains routes of multiple nets with target wire lengths for single layer routing grid with obstacles. CAFE router extends the route of each net from a terminal to the other terminal greedily so that the wire length of the net approaches its target wire length. Experiments show that CAFE router obtains the routes of nets with small length error in short time.

Refereed Proceedings Papers

[kohira-02:2010]

K. Shinoda, Y. Kohira, and A. Takahashi. Single-Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing. In 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2010), pages 278-283, October 2010.

In recent Printed Circuit Boards (PCB), the design size and density have increased, and the improvement of routing tools for PCB is required. Although there are several routing tools that generate high-quality global routings when only horizontal and vertical segments are used, PCB designers are not satisfied with these tools because high-density PCBs require segments that have arbitrary directions. In this paper, we propose a routing method that maintains the advantages of tools that use horizontal and vertical segments only, while handling higher density designs by using 45-degree segments to locally relax the routing density.

[tsuka-01:2010]

T. Tsukahara, T. Tsushima, and H. Ito. Evolution of Transceiver Architectures toward Software-Defined and Cognitive Radios (Invited Paper). In 2010 Int'l Conference on Solid State Devices and Materials (SSDM), pages pp. 99-100, 2010.

The history of RF transceiver architectures is discussed, touching on new circuit technologies such as complex quadrature modulators. Finally, recent technology trends of RF circuits for Software-Defined and Cognitive Radios are overviewed.

[tsuka-02:2010]

T. Tsukahara, H. Ito, and T. Tsushima. Evolution of Low-Power CMOS RF Transceivers (Invited Paper). In 2010 Asia-Pacific Radio Science Conference (AP-RSAC), pages CBDFK1, 2010.

The history of CMOS RF circuits is discussed, touching on new low-IF receivers using complex filtering. Finally, recent technology trends of low-power CMOS RF circuits are overviewed.

Unrefereed Papers

[kohira-03:2010]

Y. Kohira and A. Takahashi. [Invited Talk] Length-Matching Routing on Single Layer for PCB Routing Design. In IEICE Technical Report (VLD2010-47), volume 110, pages 31-36, September 2010.

[kohira-04:2010]

K. Shinoda, Y. Kohira, and A. Takahashi. A Congested Area Specification for Single Layer Printed Circuit Board Routing. In IEICE Society Conference, volume A, page 66, September 2010.

[kohira-05:2010]

K. Shinoda, Y. Kohira, and A. Takahashi. An Efficient Congested Area Specification and Congestion Relaxation by 45 Degree Line for Single Layer Printed Circuit Board Routing. In IEICE Technical Report (VLD2010-9), volume 110, pages 79-84, May 2010.

[kohira-06:2010]

Y. Kohira and A. Takahashi. An Evaluation of Clock Tree Based on Clustering in General-Synchronous Framework. In IEICE Society Conference, volume A, page 63, September 2010.

[tsuka-03:2010]

T. Tsushima and T. Tsukahara. Design of a High-Precision Complex Quadrature Modulator. In The Papers of Technical Meeting on Electronic Circuits, IEE Japan, 2010.

[tsuka-04:2010]

T. Tsushima and T. Tsukahara. A High-Precision Complex Quadrature Modulator. In The 2010 IEICE Society Conference, 2010.

Grants

[tsuka-05:2010]

T. Tsukahara. Commissioned Research Fund from ADVANTEST Corporation, 2010.

Academic Activities

[kohira-07:2010]

Y. Kohira, April 2010.

Program Committee Member, 23rd Workshop on Circuits and Systems in Karuizawa, IEICE

[tsuka-06:2010]

T. Tsukahara, 2010.

Member of the IEICE Electronics Society Technical Committee on Integrated Circuits and Devices

Patents

[tsuka-07:2010]

T. Tsukahara. Complex Quadrature Modulator and Demodulator, and Applicable Quadrature Mixers, July 2010.

Ph.D., Master and Graduation Theses

[fujii-01:2010]

Taiki Konno. Graduation Thsisi: Achieving accurate robotic arm control using a physics-based simulator, School of Computer Science and Engineering, March 2011.

Thesis Adviser: R. Fujii

[fujii-02:2010]

Hitoshi Haga. Graduation Thesis: Person identification based on handwritten hiragana, School of Computer Science and Engineering, March 2011.

Thesis Adviser: R. Fujii

[tsuka-08:2010]

Takashi Ishizaka. Master Thesis: An Opampless Amplifier Suitable for High-Speed Pipeline ADCs, Graduate School of Computer Science and Engineering, March 2011.

Thesis Adviser: T. Tsukahara

[tsuka-09:2010]

Satoru Hanzawa. Graduation Thesis: Design of Second-Order AntiAliasing Windowed-Integration Samplers, School of Computer Science and Engineering, March 2011.

Thesis Adviser: T. Tsukahara

[tsuka-10:2010]

Yuya Maeda. Graduation Thesis: A Study of Stacked-FET Power Amplifiers in Standard CMOS Technology, School of Computer Science and Engineering, March 2011.

Thesis Adviser: T. Tsukahara

[tsuka-11:2010]

Kazuto Hirata. Graduation Thesis: Noise Canceling Techniques for Low-Noise Amplifiers, School of Computer Science and Engineering, March 2011.

Thesis Adviser: T. Tsukahara

[tsuka-12:2010]

Hideyuki Ito. Master Thesis: An Integration Sampler with Embedded Higher-Order FIR Filtering for SDR Receivers, Graduate School of Computer Science and Engineering, March 2011.

Thesis Adviser: T. Tsukahara

Others

[tsuka-13:2010]

T. Tsukahara. Seminar: Basics and Applications of CMOS Analog RF Circuit Design. J-TECHNO INC, Aug. 2010.

[tsuka-14:2010]

T. Tsukahara. Seminar: Design of CMOS RF Circuits. Technological Media Center, Sept. 2010.

[tsuka-15:2010]

T. Tsukahara. History and Future Trends of CMOS RF-IC Research and Development -Expectations for Young Researchers. Lecture for Graduate School of Osaka Univ., June 2010.

[tsuka-16:2010]

T. Tsukahara. Seminar: History and Future Trends of CMOS RF-IC Research and Development. Advanced Analog Technology Seminar (Osaka Univ.), Oct. 2010.

[tsuka-17:2010]

T. Tsukahara. Seminar: IT Wireless Communication Technologies. Aizu Monozukuri Gijuku, Jan. 2011.

[tsuka-18:2010]

T. Tsukahara. CMOS RF Integrated Circuits -Overview and Perspective. Special Open Lectures on 'Beyond CMOS' (Univ. of Aizu), April 2010.