Toshiaki Miyazaki
Professor
Satoshi Nishimura
Associate Professor
Hiroshi Saito
Assistant Professor
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Toshiaki Miyazaki Professor |
Satoshi Nishimura Associate Professor |
Hiroshi Saito Assistant Professor |
The following researches are progressed in Computer Organization Laboratory:
Toshiaki Miyazaki:
has mainly two topics as follows:
Die-hard sensor network is a wireless sensor network that has an autonomous function alternation mechanism among sensor nodes as well as ordinary wireless sensor network capabilities such as automatic network establishment. With this mechanism, we can realized self-organized and maintenance-free sensor network systems. Its applications include surveillance of disaster-hit region, and river and forest monitoring. We are developing not only sensor-node hardware but also protocols equipped to the sensor node.
Custom Computing is a research field to realize a dedicated hardware using programmable logic devices such as FPGAs (Field Programmable Gate Arrays) in order to solve a give problem effectively. We focused on two applications; BLAST accelerator and 3D-DCT.
BLAST accelerator: Basic Local Alignment Search Tool (BLAST) is one of the most popular sequence alignment tools. Sequence alignment is used to extract similar parts of the input protein (or DNA) sequence from protein (or DNA) databases, in order to investigate biological evolution and genomic genealogy. It is a very important and difficult task in bioinformatics. Although BLAST is well tuned to effective sequence alignment, the performance is still not enough to deal with the rapid growing of the databases. BLAST consists of three steps: query words and neighborhood word list creation (step 1), word-hit search and ungapped extension (step 2), and gapped extension (step 3). We are developing a hardware accelerator for BLAST to mainly speedup the steps 2 and 3, which are time consuming processes. The accelerator is implemented in an FPGA to confirm the performance. According to the evaluation results, the execution time of the proposed two-hit circuit is 0.1 ms when the input database length is 6815, while that of original BLAST is about 143 ms.
Array processor for 3D-DCT: Collaborated with the Distributed Parallel Processing Laboratory in the University of Aizu, a 3D array processor for 3D-DCT was designed. In addition, the prototype system was implemented using FPGAs to evaluate the feasibility of the architecture.
Satoshi Nishimura:
Hardware for realistic image synthesis,
Computer architecture for computer graphics,
Reconfigurable hardware for multimedia applications, and
Realtime systems for computer music
Hiroshi Saito:
Our research interests are design of asynchronous circuits and its automation. Asynchronous circuits are circuits where circuit components are controlled by pairs of local handshake signals instead of a global clock signal. Because of the absence of a global clock signal, asynchronous circuits are low power and low electromagnetic interference compared to synchronous counter parts which use global clock signals. Our research topics are as follows.
Synthesis of asynchronous circuits from a behavioral model specified by C language
Design of low power and low electromagnetic interference asynchronous circuits
Synthesis of network-on-chip architecture from a behavioral model
H. Saito, N. Hamada, T. Yoneda, and T. Nanya. A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. In Proc. International Symposium on Circuits and Systems, pages 925-928, 2010.
This paper proposes a floorplan method for asynchronous circuits with bundleddata implementation on FPGAs (Field Programmable Gate Arrays). The proposed method minimizes the delay of the control circuit while considering timing constraints required for bundled-data implementation. Through the implementation of the proposed method, this paper evaluates the proposed method in terms of performance and area for generated floorplans.
T. Miyazaki and D. Shitara. Automatic Damaged-Function Alternation among Wireless Sensor Nodes. In Proc. 6th International Conference on Networked Computing and Advanced Information Management (NCM2010), pages 557-562, August 2010.
We propose a distributed algorithm for function alternations, which enables sensor nodes to take over the damaged functions of their neighboring sensor nodes dynamically in a wireless sensor network. In this paper, after introducing the concept of the function alternation, the algorithm is explained in detail with some evaluation results. Comparing the results obtained using the proposed algorithm with those obtained using non-function alternation methods shows that the proposed algorithm makes the initial functionality of each sensor function sustainable even if some sensor nodes are damaged.
Y. Endo and T. Miyazaki. Sensor Node Localization Using Weighted and Iterative Maximum Likelihood. In Proc. IEEE Sensors 2010 Conference (Sensors 2011), pages 2033-2036, November 2010.
We propose a localization method based on an enhanced maximum likelihood (ML) method, which uses the probability density function of radio signal strength indicators (RSSIs). ML is a method used for estimating node location with high accuracy. However, it often requires a large number of anchor nodes, which results in a high cost. To solve this problem, we introduce two key features into the ordinary ML method: iterative multilateration and certainty weight. The former enables the localization of nodes, which cannot directly obtain sufficient information from anchors to estimate their own location, by using the neighboring nodes with already estimated locations as pseudo-anchors (PAs). The latter provides high accuracy by weighting the location of the PA depending on its certainty. The proposed method performs localization in a distributed manner and has high scalability. The evaluation results show that our method can estimate many node locations with a higher accuracy than the original ML.
T. Miyazaki, D. Shitara, Y. Endo, Y. Tanno, H. Igari, and R. Kawano. Die-hard Sensor Network: Robust Wireless Sensor Network Dedicated to Disaster Monitoring. In Proc. ACM The 5th International Conference on Ubiquitous Information Management and Communication (ICUIMC2011), page http://doi.acm.org/10.1145/1968613.1968678, February 2011.
In this paper, a new type of wireless sensor network system, called die-hard sensor network, is described. The system can automatically monitor a disaster-hit region by scattering many sensor nodes in the region. To realize the system, three new mechanisms have been developed. If a sensor node is unable to perform certain functions, the first mechanism-function alternation-enables its neighboring sensor nodes to automatically take over these functions. Once our system is deployed, it performs uninterrupted surveillance of the disaster-hit region through this mechanism even if some of the sensor nodes suddenly die. The second mechanism is a multi-sink and multi-hop data transfer protocol that realizes reliable data transfer. The third mechanism is sensor node localization. The locations of almost all scattered sensor nodes can be estimated using only a few anchors, i.e., nodes whose positions are known. In this paper, we explain each novel mechanism, present some evaluation results, and introduce a prototype system that employs the mechanisms.
J. Terazono, H. Fukuhara, R.Fujita, I. Koseda, T. Miyazaki S. Saito, and T. Hayashi. Service Oriented Architecture realized by a Messaging Network. In Proc. the 12th IEEE/IFIP Network Operations and Management Symposium (NOMS 2010), pages 934-937, April 2010.
This paper introduces an approach to realize service-oriented architecture (SOA) governance using a messaging network. The proposed solution uses a messaging network with a structured overlay. The messaging network is XML-based, and is an actual implementation of a content-based network. The proposed scheme provides a network-centric approach to ensure SOA governance by use of a common proactive scheme on the network infrastructure.
D. Shitara, T. Miyazaki, and H. Igari. A Function Alternation Algorithm for Wireless Sensor Networks. In Proc. IEEE AINA2010 Workshop, pages 650-655, April 2010.
We propose a distributed algorithm to realize an automatic function alternation among sensor nodes. With this algorithm, the function of a damaged sensor node is dynamically taken over by a neighboring sensor node in order to maintain the initial functionality of a wireless sensor network. Each sensor node calculates an indicator value that represents the node's suitability as a candidate to alternate the function of the damaged node. By exchanging this indicator value with other neighboring nodes, the sensor node with the largest indicator value actually takes over the function of the damaged node. In this paper, after describing the function alternation algorithm, an application for sensing function alternation is introduced along with some evaluation results. Simulation results show that our algorithm can maintain a balanced distribution of sensing functions even when some sensor nodes are damaged.
S. G. Sedukhin, A. S. Zekri, and T. Miyazaki. Orbital Algorithms and Unified Array Processor for Computing 2D Separable Transforms. In Proc. 39th International Conference on Parallel Processing Workshops (ICPPW, MCNOC2010), pages 127-134, September 2010.
The two-dimensional (2D) forward/inverse discrete Fourier transform (DFT), discrete cosine transform (DCT), discrete sine transform (DST), discrete Hartley transform (DHT), discrete Walsh-Hadamard transform (DWHT), play a fundamental role in many practical applications. Due to the separability property, all these transforms can be uniquely defined as a triple matrix product with one matrix transposition. Based on a systematic approach to represent and schedule different forms of the n n ? n matrix-matrix multiply-add (MMA) operation in 3D index space, we design n matrix-matrix multiply-add (MMA) operation in 3D index space, we design new orbital highly-parallel/scalable algorithms and present an efficient n new orbital highly-parallel/scalable algorithms and present an efficient n ? n unified n unified array processor for computing any narray processor for computing any n?n forward/inverse discrete separable transform n forward/inverse discrete separable transform in the minimal 2n time-steps. Unlike traditional 2D systolic array processing, all n2 register-stored elements of initial/intermediate matrices are processed simultaneously by all n2 processing elements of the unified array processor at each time-step. Hence the proposed array processor is appropriate for applications with naturally arranged multidimensional data such as still images, video frames, 2D data from a matrix sensor, etc. Ultimately, we introduce a novel formulation and a highly-parallel implementation of the frequently required matrix data alignment and manipulation by using MMA operations on the same array processor so that no additional circuitry is needed.
Y. Tanno and T. Miyazaki. Decentralized Multi-Sink Data Transfer Protocol for Wireless Sensor Networks. In Prof. IEEE AINA2010 Workshop, pages 319-324, March 2011.
In this paper, we propose a multi-sink data transfer protocol for wireless sensor networks, called negotiation-based multi-sink data transfer (NMDT). NMDT is based on the packet flooding method, but the direction of packet flooding in each sensor node is dynamically controlled, taking into consideration the network traffic around the sensor node. Thus, stable sensed data transfer and collection can be performed without packet collisions. After explaining NMDT in detail, we present some evaluation results. According to the evaluation results, NMDT can aggregate sensed data from the sensor nodes by more than 25% as compared to the ordinary flooding method.
H. Saito. [Invited paper] Design of Asynchronous Circuits with Bundled-data Implementation on FPGA. In IEICE RECONF Technical Report, pages 157-162, 2011.
H. Naohiro and H. Saito. Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-data Implementation. In Design Gaia, pages 137-142, 2010.
Y. Tanno and T. Miyazaki. FA multi-sink data transfer protocol for wireless sensor networks. In IEICE Society Conference, volume BS-5-3, September 2009.
D. Shitara and T. Miyazaki. An Algorithm for Multiple SensingFunction Alternations among Neighboring Sensor Nodes. In IEICE General Conference, volume B-20-2, March 2010.
Y. Ikegaki, N. Takeishi, T. Miyazaki, and S. Sedukhin. A 3-D Array Processor Tuned to 3-D DCT. In IEICE Technical Report, volume FIIS-09260, June 2009.
Y. Ikegaki, H. Igarashi, T. Miyazaki, and S. Sedukhin. An effective data I/O mechanism utilizing FIFOs for an array processor. In IEICE Technical Report, volume RECONF2009-61, Jan. 2010.
D. Shitara and T. Miyazaki. Function Alternation Algorithm in Wireless Sensor Networks. In IEICE Society Conference, volume B-7-31, September 2009.
H. Igari and T. Miyazaki. An Effective OTAP Method for Multiple Sensor Nodes by Reducing Redundant Packets. In IEICE General Conference, volume B-20-1, March 2010.
Y. Endo and T. Miyazaki. Iterative Maximum Likelihood Localization for Wireless Sensor Nodes. In IEICE General Conference, volume B-20-45, March 2010.
Y. Ikegaki, T. Miyazaki, and S. Sedukhin. An FPGA Implementation of a Pipelined Array Processor Dedicated to 3D-DCT. In IEICE General Conference, volume D-6-2, March 2010.
J. Tazawa, Y. Ikegaki, S. Ishikawa M. Sato, and T. Miyazaki. Highspeed Circuit for Gibbs Sampling. In IEICE General Conference, volume D-6-3, March 2010.
Y. Tanno and T. Miyazaki. Evaluations of Negotiation-based Multisink Data Transfer Protocol. In IEICE General Conference, volume B-20-20, March 2010.
H. Saito. Ministry of Education Scientific Research Fund, 2009-2011.
T. Yoneda, M. Imai, A. Matsumoto, and H. Saito. Core Research for Evolutional Science and Technology of Japan Science and Technology Corporation, 2008-2013.
T. Miyazaki. JST A-STEP Feasibility Study, 2010.
T. Miyazaki. Kayamori Foundation of Informational Science Advancement, 2010-2011.
H. Saito, 2010.
Technical Program Committee, 5th International Symposium on Embedded Multicore Systems-on-Chip, IEEE
H. Saito, 2010.
Associate Editor, IPSJ Transactions on System LSI Design Methodology
H. Saito, 2010.
Technical Program Committee, Asia South Pacific Design Automation Conference, IEEE/ACM
T. Miyazaki, 2010.
General Chair, MCSoC-10 (IEEE 4th International Symposium on Embedded Multicore Systems-on-Chip), IEEE
T. Miyazaki, 1986 present. Member, IPSJ
T. Miyazaki, 2010.
Steering committee member, Technical Group for Reconfigurable Systems (RECONF), IEICE
T. Miyazaki, 2010.
Steering Committee Member, CIT2010 (10th International Conference on Computer and Information Technology), IEEE
T. Miyazaki, 2010.
Steering committee member, Technical Group for Function Integrated Information System (FIIS), IEICE
T. Miyazaki, 2010.
Technical Program Committee Member, UUWSN2010 (The International Workshop on Ubiquitous UnderWater Sensor Network 2010), IEEE
T. Miyazaki, 2010.
Reviewer, IEEE Transactions on SMCB
T. Miyazaki, 1984 present. Member, IEICE
T. Miyazaki, 1988 present. Member, IEEE (CAS, ComSoc, CS)
T. Miyazaki, 2010.
Reviewer, IEICE Transactions on Communications
Minoru Iizuka. Graduation thesis: An ASIC Design Support System for Asynchronous Circuits with Bundled-data Implementation, School of Computer Science and Engineering, March 2011.
Thesis Adviser: H. Saito
Hideki Katabami. Graduation thesis: Designs of OCP Compliant NoC for FPGA, School of Computer Science and Engineering, March 2011.
Thesis Adviser: H. Saito
Asuka Tanaka. Graduation Thesis: Accelerating Gapped Extension part with Traceback in BLAST using Dedicated Hardware, School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Yuki Ikegaki. Master Thesis: 3D-orbital Array Processor Architecture for 3D-DCT and Its System Implementation on an FPGA, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Yuuki Torii. Master Thesis: Peer-to-Peer Virtual Private Network Establishing Single Virtual Subnet, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Yuuki Tanno. Master Thesis: Distributed Data Transfer Protocol for Multi-Sink Wireless Sensor Networks, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Yuki Kasama. Graduation Thesis: Multi-Human Tracking in a Room Using Infrared Sensors, School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Shizuka Ishikawa. Graduation Thesis: Hardware-based Acceleration of Word-hit Part in BLAST, School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Satoshi Watanabe. Graduation Thesis: Implementation of SoftwareHardware Interaction for a 3D Array Processor Using PCI Interface, School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Hidenori Igari. Master Thesis: Remote Configuration of Sensor Nodes Using Wireless Communications, Graduate School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Miyuki Sato. Graduation Thesis: An FPGA Implementation of Continuous Dynamic Programming Using Ring Array Architecture, School of Computer Science and Engineering, 2011.
Thesis Adviser: T. Miyazaki
Liang Zhao. Master Thesis: A Statistical Method Extracting Daily Behavior of a Solitary from Data Continuously Aggregated by Sensors Equipped in Rooms, Graduate School of Computer Science and Engineering, September 2010.
Thesis Adviser: T. Miyazaki
Hiroshi Igashima. Graduation Thesis: An Effective Implementation of Sensor Node Localization Method Based on Maximum-Likelihood Using Received Signal Strength Indicator, School of Computer Science and Engineering, March 2011.
Thesis Adviser: T. Miyazaki
Akira Sato. Graduation Thesis: Finger recognition with multi-colored markers, University of Aizu, 2011.
Thesis Adviser: S. Nishimura
Yoshiaki Hagane. Master Thesis: A GPU-Based Direct Solver for LargeScale Sparse Linear System, University of Aizu, 2011.
Thesis Adviser: S. Nishimura
Masaaki Yoshizawa. Master Thesis: Score Tracking Based on Musical Audio Signals, University of Aizu, 2011.
Thesis Adviser: S. Nishimura
Kousuke Sato. Graduation Thesis: A scalable VLSI design for Mersenne Twister on FPGA, University of Aizu, 2011.
Thesis Adviser: S. Nishimura
Takanori Sato. Graduation Thesis: An assist tool for fixed-point digital signal processing, University of Aizu, 2011.
Thesis Adviser: S. Nishimura
Yuki Yonekawa. Graduation Thesis: Photon-Mapping Rendering Processing on GPU, University of Aizu, 2011.
Thesis Adviser: S. Nishimura
Hikaru Sakai. Graduation Thesis: Implementation of a Vector Generator for Real-Time Ray Tracing, University of Aizu, 2011.
Thesis Adviser: S. Nishimura
2011 THE UNIVERSITY OF AIZU ALL RIGHTS RESERVED