Annual Review 2011 > Division of Computer Engineering

Adaptive Systems Laboratory

Kenichi Kuroda


Junji Kitamichi

Associate Professor

Yuichi Okuyama

Assistant Professor

Ben Abdallah Abderazek

Assistant Professor

The academic area of this laboratory mainly covers computer design methodology. Reconfigurable computing, formal verification, network on a chip, and educational course design for VLSI are the major themes of this lab.

Short history of the Lab.:

"Computer Education Lab." started in 1993.

1993-1998 Prof. A. Taubin 2000- Prof. K. Kuroda

2002- Prof. J. Kitamichi joined.

2005- Prof. Y. Okuyama joined.

2007- Prof. A. Ben joined.

2008- The title of the laboratory changed to "Adaptive Systems Lab.".

Members of our laboratory are four professors, 9 master program students, and 6(B4)+7(B3) graduate thesis students.


We have been developing an education program of VLSI design based on VDEC (VLSI Design and Education Center) support. VDEC offers various kinds of design tools without license costs and accepts chip fabrication orders in low price. This program was started as a joint research with Prof. Shima, who left from this university in 2004, in Computer Architecture Laboratory in 2001. Web-based manuals for HDL design, verification, and layout tools have been developed and are being updated depending on VDEC support tools every year. Colaborating with Computer Organization Lab. and Logic Circuit Design Lab., we are establishing educational materials on embedded systems and FPGA-based design courseware.

Research: Recently, we are now focusing on the higher level design circumstances, such as UML, SystemC, and other HDLs. We developed a new design flow from SFL (one of the HDLs) to SystemC for improving the design efficiency. As to the VDEC-based synchronous circuit technology, various applications such as bio-informatics and network security have been surveyed.

We started a new approach to high performance computing systems with reconfigurable devices collaborating with the RIKEN research group, the PROGRAPE Project. The target of this project is “ Desktop Supercomputing System ”. “ Desktop ”means low-cost with commercially available FPGAs and PCs. We have been developing interface circuits and new applications such as fluid dynamics, data mining, and others. In collaboration with Prof. S. Sedukhin (Distr. Parallel Proc. Lab.), we have been developing a prototype of RapidMarix Processor System, which is a kind of torus array system specified for high performance matrix operation.

We also started a new approach to high performance computer architecture, "Queue Processor" and Network-on-Chip Architecure based on Prof. Ben's research background.

Members of the Computer Education Laboratory

Prof. Kenichi Kuroda:

Before his coming to this university, he belonged to the NTT laboratories and he was engaged with the research on superconductor devices, SAW devices, and X-ray optics. He joined this university mid 1995. He received his Dr. Eng. from Tokyo University in 1991. After coming to this university, he had been a member of the Computer Device Lab. for 5 years and moved to Computer Education lab. in summer 2000. The lab name changed to "Adaptive systems Laboratory" in 2008. He was interested in VLSI design technology. Especially, reconfigurable device systems are the current major research direction.

Prof. Junji Kitamichi:

He received the B.S. and Ph.D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Center at Osaka University, where he was assistant professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. His research interests include formal methods for VLSI design, dynamically reconfigurable systems, heuristics and parallel algorithms for combinatorial optmization problems.

Prof. Abderazek Ben Abdallah:

He received his BTS degree from Sfax University in 1990. The BE, ME degrees from HUST Univ. in 1994 and 1997 respectively. In 2002, he received his Ph.D. degree from the Univ. of Electro-communications. From 2002 to 2007, he was a research associate at the Univ. of Electro-communications, Graduate School of Information Systems, then Assistant Professor at the network computing laboratory. He joined the Univ. of Aizu in 2007. His research interests span the areas of computer systems, embedded systems, and VLSI.

Prof. Yuichi Okuyama:

He was born in 1975. He received the M.S and Ph.D degrees in computer science and engneering from the University of Aizu in 1999 and 2002, respectively. He entered NTT Network Innovation Laboratories and was engaged with the development of PCA (Plastic Cell Architecture) devices. He joined the University of Aizu in 2005 as an assistant professor. His current interests are implementation of applications on hardware, tool development for design automation on reconfigurable device(FPGA and other devices) and design of hardware for scientific calculations.

Students :

Master Program:

M2:Mizuho Shiga, Junko Tazawa, Yukihiro Yoshida, Shoichi Igarashi, Shohei Miura, Kenichi Mori, Ryuhei Morita, Akram Ben Ahmed..

M1:Hayato Mamae, Yumiko Kimezawa, Yukihiro Kotani, shota Niki, Shuta Yamamoto, Ben A. Achraf.

Graduation Thesis Students:

B4:Tomotaka Kasahara, Ryosuke Kaji, Ryuya Okada, Kazuji Kobayashi, Yoshiaki Kondo, Toshihiro sato, Taichi Hasegawa, Yoshuke Haraguchi.

B3:Toshiichi Idonuma, Takaaki ouchi, Yya Otsuka, Makoto Yoshizawa, Toru Hasegawa, Shu Endo, Tokimasa Shirai.

Refereed Journal Papers

[benab-01:2011, kuroken-01:2011]

A. Ben Abdallah, M. Masuda, A. Canedo, and K. Kuroda. Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture. The Journal of supercomputing, 57(3):314-338, Sept. 2011.

This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computationbased processor. The instructions of a queue processor implicitly read and write their operands making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore. For a set of numerical benchmark programs our compiler extracts more parallelism than the optimizing compiler for a RISC machine by a factor of 1.38. Through the use of QueueCore’s reduced instruction set, we are able to generate 20embedded RISC processors.


M. Sakai, Y. Okuyama, and D. Wei. Separation of EEG and ECG components based on wavelet shrinkage and variable cosine window. Journal of Medical Engineering & Technology, 36(1-2):135-143, 2012.

During ambulatory monitoring, it is sometimes required to record an electroencephalogram (EEG) and an electrocardiogram (ECG) simultaneously. It would be ideal if both EEG and ECG could be obtained with one measurement. Here, we introduce an algorithm that combines the wavelet shrinkage and variable cosine window operation to separate the EEG and ECG components from an EEG signal recorded with a noncephalic reference (NCR). Evaluation using simulated data and actual measured data showed that accurate frequency analysis of EEG and an RR detection-based heart rate analysis were feasible with our proposed algorithm, which improved the signal-averaging based algorithm so that ECG components containing ectopic beats can be applied.

Refereed Proceedings Papers

[kitamiti-01:2011, kuroken-02:2011, okuyama-02:2011]

Syuhei Igari, Junji Kitamichi, Yuichi Okuyama, and Kenichi Kuroda. Proposal of a Dynamically Reconfigurable Processor Architecture with Multi-Accelerator. In Proc. of IPEmbedded System Conference & Exhibition (IP-SOC 2011), page AD 4, Dec. 2011.

The progress of LSI manufacturing technology has realized large-scale systems on a single chip, such as a System on a Chip(SoC) in recent years. In the field of embedded systems, the SoC has problems related to increasing in the scale of circuits and reducing the design costs, due to many types of application specific hardware modules. We expect that these problems can be overcome by reconfigurable devices such as Field Programmable Gate Arrays(FPGAs). Some of FPGAs can change circuit configuration dynamically while the system is running. In this paper, we propose a dynamically reconfigurable processor architecture with a multi-accelerator using Dynamic Partial Reconfiguration(DPR) technology by XILINX. The proposed architecture consists of a processor, some memories, some buses, controllers and some dynamically reconfigurable accelerators. We employ a multi-bus system and design the controllers for a dynamically reconfiguration. A JPEG encoder and decoder that are open-source IPs are used as target applications. The proposed architecture is implemented on a Virtex-6 FPGA and evaluated regarding the circuit size and reconfiguration time. The results showed that the partial reconfiguration time was small enough.

Unrefereed Papers


Naoki Shibata Keiichi Yasumoto Yosuke Wakisaka, Junji Kitamichi and Minoru Itou. Energy-efficient task scheduling method for the data center based on adjustment of program's execution time. In IPSJ SIG Techhnical Reports-HPC-130(25), 2011.


Hiroyuki Kotani and Junji Kitamichi. Porposal of Real Time OS for Multi-processor on FPGA. In IPSJ SIG Techhnical Reports-SLDM-155(28), 2012.


Yosuke Haraguchi and Junji Kitamichi. An Implementation of ARM Processor for Power Consumption Evaluation. In Proceedings if the 2012 IEICE General Conference, 2012.


Kei Itou and Junji Kitamichi. Proposal of a Self-Learning Support System for University Education based on an Object Oriented Approach. In Proceedings of PC Conference 2011, 2011.

[kuroken-03:2011, okuyama-03:2011]

Shoichi Igarashi, Ryuhei Morita, Yuichi Okuyama, Tsuyoshi Hamada, JJunji Kitamichi, and Kenichi Kuroda. Design and Implementation of a Portable Framework for PCI-Express Interface. In IEICE TEchnical Report, Reconf2011-8, pages pp.43-48. IEICE, May 2011.

In this paper, we propose a portable framework for PCI-Express interface. The proposed framework porvides DMA transter and interruption between a host PC and an FPGA board to reduce development time for acceleration board implementation. The proposed framework [rpvodes an interface circuit designed by using Altera's SOPC Builder to enhance portability. It fnctions on different Altera's FPGA boards to support PCI Express. Thus, the system is easy to be ported. The PROGRAPE system with the porposed frame work is implemented on two different size FPGA boards to evaluate portability and the performance of interparticle calculation. As a result, the new PROGRAPE system is easy to be ported to a larger FPGA board. The ported system achieves higher performcance without signifcant redesign.

[kuroken-04:2011, okuyama-04:2011]

Ryuhei Morita, Shoichi Igarashi, Yuichi Okuyama, Tsuyoshi Hamada, JJunji Kitamichi, and Kenichi Kuroda. Development of a PROGRAPE System Applying to Some FPGA Boards. In Proc. of 37th PARTHENON Workshop, pages pp.25-32. PARTHENON Society, Sep. 2011.

This paper proposes a PROGRAPE system applying to FPGA boards which equip Altera's FPGA. The PROGRAPE system is one of acceleration systems for interparticle calculation. It is applied to the N-body problem, the smoothe particle hydrodymamics (SPH) and other interparticle problems. The advantage of this accelerator is reconfigurability pipelines. Thus, the number of pipelines is optimized with target applications. However, we must redesign the FPGA specification dependet circuits when we modify the system to other FPGAs. To solve this problem, we develop a PCI-Express interface between the host PC and FPGAs. We also design a new PROGRAPE system for the PCI-Express interface and reduce GPGA specification dependent circuits. We demonstarate the gravitational N-body problem on two FPGA boards. We cost 10 hours for porting system and chieve 199 Gflops.

Academic Activities


A. Ben Abdallah, 2011.

Area Chair of the Parallel, Distributed and Multicore Computing track of the IEEE 14-th International Conference on Network-Based Information Systems (NBiS-2011)


A. Ben Abdallah, 2011.



A. Ben Abdallah, 2011.

PC members of the IEEE Symposium on Low-power and High-speed Chips (COOL Chips XI), Yokohama, April 18-20, 2012


A. Ben Abdallah, 2011.

Session Chair of the IEEE Symposium on Low-power and High-speed Chips (COOL Chips XI), Yokohama, April 18-20, 2012 (session chair).


A. Ben Abdallah, 2011.

Program co-chair of the tth International Workshop of Engineering Parallel and Multicore Systems, July 4-6, 2012, Palermo, Italy. (Program Co-chair).


A. Ben Abdallah, 2011.

Organizer of the IEEE MCSoC-12 Symposium, Sept. 20-22, 2012, The University of Aizu, Aizu, Japan. URL:


Kitamichi J., 2011.

Member. IEEE


Kitamichi J., 2011.

Member, IEICE


Kitamichi J., 2011.

Member, IPSJ


Kenichi Kuroda, 2010.

Member of IEICE Student Activity Support Committee


Kenichi Kuroda, 2010.

Member of Management Board of PARTHENON Society (NPO)


Kenichi Kuroda, 2010.

JSAP Regular member


Kenichi Kuroda, 2010.

IEICE Regular member


Kenichi Kuroda, 2010.

IPSJ Regular member


Yuichi Okuyama, April 2011.

Committee member, IEICE CPSY 2011.


Yuichi Okuyama, April 2011.

Steering committee, PARTHENON sosiety 2011.


Yuichi Okuyama, April 2011.

Regular member, JSSST 2011.


Yuichi Okuyama, April 2011.

Regular member, IPSJ 2011.

Ph.D., Master and Graduation Theses


Shohei Miura. Design of Parametrizable Network-on-Chip. Master thesis, Graduate School of Computer Science and Engineering, 2012.

Thesis Adviser: A. Ben Abdallah


Ryuya Okada. Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC. Graduation thesis, School of Computer Science and Engineering, 2012.

Thesis Adviser: A. Ben Abdallah


Kenichi Mori. OASIS Network-on-Chip Prototyping on FPGA. Master thesis, Graduate School of Computer Science and Engineering, 2012.

Thesis Adviser: A. Ben Abdallah


Tomotaka Kasahara. Performance and Complexity Study of MultiQueueCore Systems. Graduation thesis, School of Computer Science and Engineering, 2012.

Thesis Adviser: A. Ben Abdallah


Akram Ben Ahmed. On the Design of 3D NoC for Manycore SoCs. Master thesis, Graduate School of Computer Science and Engineering, 2012.

Thesis Adviser: A. Ben Abdallah


Shoichi Igarashi. A Design Framework for Highly-Portable PCIExpress Inteface FPGA Boards. Master Thesis, Graduate School of Computer Science and Engineering, 2012.

Thesis Adviser: Kenichi Kuroda


Shohei Morita. A Retargetable PROGRAPE System with a PCIExpress Framework. Master thesis, Graduate School of Computer Science and Engineering, 2012.

Thesis Adviser: Kenichi Kuroda


Junko Tazawa. Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programming. Master thesis, Graduate School of Computer Science and Engineering, 2012.

Thesis Adviser: Y. Okuyama


Ryosuke Kaji. cceleration of Accumulated Value Calculation for Two-Dimentional Continuous Dynamic Programming with GPGPU. Graduation thesis, School of Computer Science and Engineering, 2012.

Thesis Adviser: Y. Okuyama


Toshihiro Sato. valuation of Error Bound and Processing Time in Approximated Nearest Neighbor Searching for Nonlinear Projective Algorithm. Graduation thesis, School of Computer Science and Engineering, 2012.

Thesis Adviser: Y. Okuyama


Yukihiro Yoshida. An acceleration method of Two-dimensional Continuous Dynamic Programming with Multi-core processor and GPGPUs. Master thesis, Graduate School of Computer Science and Engineering, 2012.

Thesis Adviser: Y. Okuyama



A. Ben Abdallah. I was an invited Professor at the following two foreign Universities: (1) Huazhong Univ. of Science and TEch nology, Wuhan, China, March 2012. I gave the course: Distributed Computing; (2) Hong Kong Univ. of Science and TEchnology, Hong Kong, China. I gave lectures entitled: Networkon-Chip KUST to graduate students., 2012.

Senior Associate Professor Abderazek Ben Abdallah of the Adaptive Systems Laboratory was invited to Huazhong University of Science and Technology, China, as a lecturer of an intensive course entitled Distributed Computing . During his visit to HUST for about 2 weeks from March 1, he gave a series of lectures on the design of distributed systems to about 70 students in the School of Software Engineering. Lectures covering various topics such as software architecture, computer communication and process synchronization were provided to help students understand the fundamental concepts and techniques in distributed computing. By the end of the course, the students reached their goal to develop a complete system using techniques such as process, thread management, synchronization and sockets/RPCs. He also visited Hong Kong University of Science and Technology from March 25 and gave 4 lectures about Network-on-Chip to approximately 80 graduate students. At both universities, he discussed possible collaborations with the University of Aizu. Ref.