BEN ABDALLAH, ABDERAZEK
Senior Associate Professor (上級准教授)
PhD (2002), UEC @ Tokyo; M.S.(1997) & B.S.(1994), HUST Univ.

School of Computer Science and Engineering,
Adaptive Systems Laboratory
The University of Aizu,  Aizu-Wakamatsu City,
Fukushima 965-8580, Japan
Office: RQ 206-B, 
E-Mail: benab(at)u-aizu.ac.jp
Research Interests
 		System design and its design support for parallel systems, especially: heterogeneous multi-core architectures for complex, data-intensive applications; Network-on-chip;
power and energy management; and CPU/GPU convergence.
Teaching -Undergraduate: Embedded Systems; Computer System Engineering; System-on-Chip Design,; Computer Architecture Ex., Logic Circuit Design Ex.
-Graduate: Advanced Computer Organization; Embedded Real-Time Systems; Multicore Computing; Distributed Computing
Visiting Professor at AUST Univ. (2008/09/10), KUST Univ. (2010/11/12), and HUST Univ. (2011/12).
Research
Summary
Current research focuses on massively integrated heterogeneous multi-core systems design for complex, data-intensive computation applications. I am also investigating on-chip networks (NoCs), especially issues
related to novel topologies and routing algorithms. To address these challenges, we are  considering several approaches:
  • Research on Network-on-Chip for efficient data transmission of data-intensive multimedia applications (i.e. ref., MS theses 2011 (thesis1, thesis2);  BWCCA-2010 papers (slides1, slides2)
  • New on-chip communication synthesis methodology (i.e. ref. TJAS2006's paper, slides; ICPP2007's paper slides)
  • Development of low-power parallel Queue processor and its integrated development environment for domain-specific applicatios (i.e. ref. 2011 MS thesis slides, thesis)
  • Design and evaluation of new dual-mode processor architecture (i.e. ref. 2011 MS-11' slides, thesis)
  • Development of prallelizing compiler (i.e. ref. ICPPW2009's paper slides, 2011 MS-11' slides, thesis )
  • Prototyping of shared memory Multi-QueueCore processor (i.e. ref. 2011 GT' slides)
  • Application-specific multicore SoC (i.e. ref. 39th ICCPP2010's paper slides , IJCR's paper)
Past research has focused on research about architectural optimization of super-scalar processors, dynamic scheduling, and non-conventional parallel computing models.
To address these challenges, several approaches were considered:
  • Natural Instruction-Level-Parallelism aware compiler development  (i.e. ref. Jnl. of Supercomputing's 2011 paper , Jnl. of Parallel Computing's 2009 paper) 
  • New low-power, high-performance parallel queue processor architecture (i.e. ref. Jnl. of Parallel and Distributed Computing's 2008 paper)
  • New dynamic fast issue mechanism for dynamically scheduled super-scalar processors (i.e. ref. IEICE transactions' 2000 paper )
  • Research on Hybrid Processor Architecture (i.e. ref. PhD dissertation, 2002).
  • Research on Hybrid Parallel Programming for SMP Clusters (i.e. ref. IPSJ transaction's 2004 paper).
Grants:
  • Distributed Shared-Buffers Network-on-Chip for High-performance Many-core Systems, CRF- Competitive Research funding (2011-2012).
  • Smart Embedded Microchip System for Elderly Monitoring, CRF- Competitive Research funding (2008-2010).
  • Study of Low Latency Interconnection Networks using Predictive Switches, NII Joint Research funding (2006-2007).
  • Research on High-Performance, Low Power Queue Processor (UEC-XB2004-2005)
  • Dual-Mode Processor Architecture (UEC-XB2002-2003 )
Awards
  • National Prize for Scientific Research and Technology, 2010. 
  • Best Paper Award at BWCCA-2010 Conference, Fukoka, Japan, 2010.
  • Best Presentation Award at FAN-2009  Conference, Japan, 2009. 
  • Best Paper Award at the PDCAT-2007 Conference, Australia, 2007.
  • Certificate of  Merit from HUST University, 1993 &1994.

Publications
Reviewed Journal and Conference papers
  • A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda,"Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture", The Journal of supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.
  • A. Canedo, A. Ben　Abdallah, and M. Sowa, "Compiling for Reduced Bit-Width Queue Processors", The Journal of Signal Processing Systems, Volume 59, Number 1, 45-55, 2010.
  • A. Ben Abdallah, A. Canedo, T. Yoshinga, and M. Sowa, "The QC-2 Parallel Queue Processor Architecture", Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.
  • A. Ben Abdallah, et. all., "Network on Chip Synthesis Methodology for Domain Specific Multicore SoCs", submitted to the IEEE Transaction on Parallel and Distributed System.
  • A. Canedo, A. Ben　Abdallah, and M. Sowa, "Efficient Compilation for Queue Size Constrained Queue Processors", The Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.
  • M. Akanda, A. Ben　Abdallah, and M. Sowa, "Dual-Execution Mode Processor Architecture", Journal of Supercomputing, Vol. 44, No. 2, pp. 103-125, 2008.
  • A. Canedo, A. Ben　Abdallah, and M. Sowa, "A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model", Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007
  • A. Ben　Abdallah, and M. Sowa, "Advanced Power Management Techniques for Mobile Communication Systems", Journal of Computer Research, Vol. 14, No.2 , pp. 109-128, 2007
  • A. Canedo, A. Ben　Abdallah, and M. Sowa, "Design and Implementation of a Queue Compiler", Journal of Microprocessors and Micro systems, Vol. 33, Issue 2, pp. pp. 29-138, 2009.
  • Mushiq Akanda, A. Ben　Abdallah, and M. Sowa, "Dual-Execution Mode Processor Architecture for Embedded Applications", Journal of Mobile Multimedia, Vol. 3, No. 4, pp. 347-370, 2007.
  • A. Canedo, A. Ben　Abdallah, and M. Sowa, "Compiler Support for Code Size Reduction using a Queue-based Processor", Transactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009.
  • A. Ben　Abdallah, T. Yoshinaga, and M. Sowa, "High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core", Journal of supercomputing, Vol. 38, Number 1, pp. 3-15, 2006.
  • Y. Nakanisi, A. Canedo, A. Ben　Abdallah, and M. Sowa, "Optimizing Reaching Definitions Overhead in Queue Processors", Journal of Convergence Information technology, 2007, Vol. 2, No. 4, pp. 36-40, 2007.
  • A. Ben　Abdallah, Sotaro Kawata, and M. Sowa, "Design and Architecture for an Embedded 32-bit QueueCore", Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.
  • T. Viet, T. Toshinaga ,A. Ben　Abdallah, and M. Sowa, "Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters", IPSJ transactions on Advanced Computing Systems, Vol.46, pp.25-37, Jan. 2005
  • M. Sowa, A. Ben　Abdallah, and T. Yoshinaga, "Processor Architecture Based on Produced Order Computation Model", Journal of Supercomputing, Vol. 32,No. 3, pp. 217-229, June 2005.
  • A. Ben　Abdallah, Mudar Sarem, and M. Sowa, "Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors", IEICE transactions on Fundamental of Electronics, Communications and computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.
  • Kenechi Mori, A. Esch, A. Ben Abdallah, K. Kuroda, Advanced Design Issues for OASIS Network-on-Chip Architecture, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010.
  • Akram Ben Ahmed, A. Ben Abdallah, K. Kuroda,Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010.  (Best Paper Award)
  • A. Ben Abdallah, Y. Haga, K. Kuroda,An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records, IEEE Proc. of the 39th he International Conference on Parallel Processing Workshop, San Diego, pp.99-103, Sept. 13-16, 2010.
  • M. Masuda, A. Ben Abdallah, A. Canedo, “Software and Hardware Design Issues for Low Complexity High-Performance Processor Architecture”, ICPP Workshops, pp. 558-565, 2009.
  • Y. Haga, A. Ben　Abdallah, and K. Kuroda, "Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing," The 19th Intelligent System Symposium (FAN 2009), pp.298-303, Sep. 2009.
  • S. Miura, A. Ben　Abdallah, and K. Kuroda, "PNoC - Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration," The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep. 2009.
  • K. Mori, A. Ben　Abdallah, and K. Kuroda, "Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA," The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009.
  • M.  Masuda, A. Canedo, A.  Ben Abdallah, "Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture," The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009.(Best Presentation Award).
  • T. Maekawa, A. Ben　Abdallah, and K. Kuroda, "Single Instruction Dual-Execution Model Processor Architecture" , Proc. IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008), pp.30-36, Dec. 2008.
  • H. Hoshino, A. Ben　Abdallah, and K. Kuroda, "Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model", IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.
  • A. Canedo, A. Ben　Abdallah, and M. Sowa, "Quantitative Evaluation of Common Sub-expression Elimination on Queue Machines", Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.
  • A. Ben　Abdallah , T Yoshinaga, and M. Sowa, "Mathematical Model for Multiobjective Synthesis of NoC Architectures", Proc. IEEE of the 36th International Conference on Parallel Processing, Sept., 2007.
  • A. Canedo, A. Ben　Abdallah, and M. Sowa, "Queue Register File Optimization Algorithm for QueueCore Processor", Proc. IEEE 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.
  • A. Ben　Abdallah, T. Yoshinaga, and M. Sowa, "Scalable Core-Based Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC (MCSoC)", Proc. IEEE 35th International Conference on Parallel Processing Workshops, Aug. 14-18th, pp. 345-352, 2006.
  • A. Canedo,A. Ben Abdallah, and M. Sowa, "An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model", Proc. of the IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007.
  • A. Canedo, A. Ben Abdallah, M. Sowa, New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP, In Proceedings of the Eight International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT'07), Adelaide, Australia, pp. 185-192, 2007. (Best Paper Award)
  • A. Canedo,A. Ben　Abdallah, and M. Sowa, "An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model", Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007
  • A. Canedo, A. Ben Abdallah, and M. Sowa, "Compiler Framework for an Embedded 32-bit Queue Processor" , Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.
  • A. Ben　Abdallah, and M. Sowa, "Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization", Proc. of Tunisia-Japan Symposium on Society, Science and Technology (TJASSST), Dec. 4-9th, 2006.
  • A. Ben　Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, "Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005.
  • M. Akanda, A. Ben　Abdallah, S. Kawata, and M. Sowa "An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture", Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 77-86, Dec. 2005.
  • A. Markovskij, A. Ben　Abdallah, S. Kawata, and M. Sowa, "Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation", Proc. of the 38th International Symposium on Microarchitecture (MICRO-38), Nov. 2005
  • A. Ben　Abdallah, Markov Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, "Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme", Proc. IEEE of the 7th High Performance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
  • Shigeta, L.-Q. Wang, N. Yagishita, A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "QJava: Integrate Queue Computational Model into Java", Proc. of the Joint Japan-Tunisia Workshop on Computer Systems and Information Technology (JT-CSIT'04), July 2004.
  • A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, "Design of Producer-Order Parallel Queue Processor Architecture", Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.
  • M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "High performance Hybrid Processor Architecture with Efficient Hardware Usability", Proc. of International workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004
  • H. Sasaki,Y. Okumura, A. Ben　Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Theoretical Evaluation of Simultaneous Multi threading Parallel Queue Processor Architecture", Proc. International Conference on Circuits/Systems, Computers and Communications, July 2004.
  • A. Ben　Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "On the Design of a Register Queue Based Processor Architecture (FaRM-rq)", Proc. of the International Symposium of Parallel and Distributed Processing and Applications (ISPA 2003), pp.248-262, July 2003.
  • L. Q. Wang, A. Ben　Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java Byte-code", Proc. of International Technical Conference in Circuits/Systems, Computers and Communications (ITC-CSCC2003), pp. 900-903, July 2003.
  • A. Ben　Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Architectural Issues in the Design of a High Performance Parallel Queue Processor", Proc. of 4th Tunisia-Japan Symposium on Science and Technology (TJASSST2003), April 2003.
  • Tao. Q. Viet, T. Yoshinaga, A. Ben　Abdallah, and M. Sowa, "A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPs", SACSIS03, pp.299-306, 2003.
  • A. Ben　Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Complexity Analysis of a Functional Assignment Register Microprocessor", Proc. of the Int. Workshop on Modern Science and Technology (IWMST02), pp.116-123, Sep. 2002.
  • A. Ben　Abdallah, K. Nikolova, and M. Sowa, "FARM-Queue Mode: On a Practical Queue Execution Model", Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, pp.939-944, July 2001.
  • Kiriuka Nikolova,A. Ben　Abdallah, and M. Sowa, "Dynamical Critical Path Parallelism-Independent Scheduling Algorithm for Distributed Computing Systems", Proc. of the International Technical Conference on Circuits and Systems, Computers and Communications, pp. 929-934, July 2001.
  • A. Ben　Abdallah, and M. Sowa, "DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor", Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT'99), pp.131-136, Oct.1999.
  • A. Ben　Abdallah, M. Sarem, and M. Sowa, "A Survey on the advances of Disc I/O performance metrics", Proc. of International Conference on Robotics, Vision and Parallel Processing, pp. 522-527, July 1999.
  • A. Ben　Abdallah, A. Kazi, and L. L. Shan, "Multi Function Interface Board for Teaching Topics and Development System", APST97, Yata, PRC. pp.134-139, Sep. 1997.
  • L. L. Shan, L. Liu, and A. Ben Abdallah, "The Master Slave Two Level Distributed Microcomputer Measuring and Monitoring System", ISMTIT, Japan, pp. 161-164, 1996
Short Conference Papers
  • A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing", Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.
  • Ta Quo Viet, T. Yoshoinaga, and A Ben Abdallah, "Performance Enhancement for Matrix Multiplication on an SMP PC Cluster", Summer United Workshops on Parallel, Distributed and Cooperative Processing, August 2005.
  • A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, "PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL", Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.
  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)", Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.
  • A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, "FaRM Queue Mode: On a Practical Queue Execution Model (QEM)", TIWSS’01, October 2001
  • A. Ben Abdallah, K. Nikolova, and M. Sowa, "FaRM-Queue Execution Model: Towards an Alternative Computing Paradigm", Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000.
  • A. Ben Abdallah, M. Sarem., and M. Sowa, "Acyclic DFG on a Queue Machine", Proc. of JSPP, Tokyo, pp.119-120, 2000.
  • A. Ben Abdallah, and M. Sarem., " Instruction Scheduling System for Super scalar Processor", JSPP, Tokyo, pp.161, Apr. 2000
  • T. Viet, T. Toshinga, A. Ben Abdallah, and M. Sowa, "Optimization for Hybrid MPI-OpenMP Programs on a Cluster of SMPs", SACSIS 2004.
  • A. Musfiquzzaman, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Queue Computation Mechanism For Parallel Execution in Parallel Queue Processor", Proc. of Information Processing Society of Japan , Vol. 60, pp. 3F-4, 2004.
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Fast, Effective Instruction Generation Algorithm For Queue-Java Compiler (QJAVAC)", Proc. of Information Processing Society of Japan, Vol.2003, No.40, pp.55-60 (2003
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "An Ambiguous Context-Free Grammar for Deterministic Parsing In Queue-Java Compiler", Proc. of Information Processing Society of Japan, Vol.2003, No.62, pp.7-12 (2003).
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M  Sowa, "QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java", Proc. of IIEICE Technical conference 2003.
  • T. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, "A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPs", Proc. of Symposium on Advanced Computing Systems and Infrastructures, pp.299-306 (2003.

Books 

  • A. Ben Abdallah, Multicore Systems-on-Chip: Practical Hardware/Software Design, 1st Ed., ISBN 978-90-78677-22-2, World Scientific Publishers, (can be ordered from Amazon), 2010, (author).
  • A. Ben　Abdallah, Multicore Systems on Chip, ISBN:978-81-7895-258-1, Signpost Publishers, 2007 (Editor and one of the authors).
Book Chapters
  • A. Ben　Abdallah, A. Canedo, and K. Kuroda, "Processor for Mobile Applications", ISBN: 978-1-60566-046-2,IGI Publishers, 2008.
  • A. Ben　Abdallah, and M. Sowa, "Efficient Design Methodology and Synthesizable Core for Multicore SoCs",ISBN: 978-81-7895-258-1, Signpost Publishers, 2007
  • A. Ben　Abdallah, and M. Sowa, "Buffer Design in Packet Switched Networks for MCSoCs Applications",ISBN: 978-81-7895-258-1, Signpost Publishers, 2007
  • A. Ben　Abdallah, and M. Sowa, "Advanced Power Reduction Techniques in Mobile Computing Systems", ISBN:1-60021-207-7, Nova Science Publishers, 2006.
  • A. Ben　Abdallah, and M. Sowa, "Power Optimization techniques for Mobile Multicore SoCs",ISBN: 978-81-7895-258-1, Signpost Publishers, 2007.

Supervised Graduate and Undergraduate theses:

  • Kenichi Mori, "OASIS Network-on-Chip Prototyping on FPGA", Master's Thesis , The University of Aizu, Feb. 2012.
  • Akram Ben Ahmed, "On the Design of 3D NoC for Manycore SoCs, Master's Thesis, The University of Aizu, Feb. 2012.
  • Shohei Miura, "Design of Parametrizable Network-on-Chip", Master's Thesis, The University of Aizu, Feb. 2012.
  • Ryuya Okada, "Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC, Graduation Thesis, The University of Aizu, Feb. 2012.
  • Tomotaka Kasahara, "Performance and Complexity Study of Multi-QueueCore Systems, Graduation Thesis, The University of Aizu, Feb. 2012.
  • Hiroki Hoshino, "Development of Parallel Processor Architecture and its Integrated Development Environment, Master's Thesis, The University of Aizu, Feb. 2011.
  • Taichi Maekawa, "Design and Evaluation of Dual Mode Processor Architecture", Master's Thesis, The University of Aizu, Feb. 2011.
  • Masashi Masuda, "Development of Parallelizing Compiler", Master's Thesis, The University of Aizu, Feb. 2011.
  • Takahiro Uesaka, "OASIS NoC Topology Optimization with Short Path Link,Graduation Thesis", The University of Aizu, Feb. 2011.
  • Shunichi Kato, "Shared Memory Multi-QueueCore Processor Design",Graduation Thesis, The University of Aizu, Feb. 2011
  • Yumiko Kimezawa, "Multicore SoC Architecture for Realtime Data Intensive ECG Processing", Graduation Thesis, The University of Aizu, Feb. 2011.
  • Yuuki Omoto,"Development Environment for Single Chip Computer intended for Queue Computing Development and Education", Graduation Thesis, The University of Aizu, Feb. 2010.
  • Haga Yasuyoshi, "Architecture and Design of Application Specific Multicore SoC", Graduation Thesis, The University of Aizu, Feb. 2010.
  • Reo Honjoya,"Development of User Friendly Assembler for Queue Computers", Graduation Thesis, The University of Aizu, Feb. 2010.
  • Mori Kenichi, "Optimizations Techniques and FPGA Prototyping of OASIS Network-on-Chip", Graduation Thesis, The University of Aizu, Feb. 2010.
  • Miura shohei, "Architecture and Design of Parameterizable Network-on-Chip", Graduation Thesis, The University of Aizu, Feb. 2010.
  • Masashi Masuda, "Graph Transformation Methods and Theoretical Performance Evaluation of FIFO Computation Models", Graduation Thesis, The University of Aizu, Feb. 2009.
  • Hiroki Hoshino, "Advanced Hardware Optimization Algorithms for High Performance QueueCore Processor Architecture", Graduation Thesis, The University of Aizu, Feb. 2009.
  • Tachi Maekawa, "Research on Hardware Design of Dual-Mode Processor Architecture", Graduation Thesis, The University of Aizu, Feb. 2009.
  • AUST University: 6 Master's theses.,
  • UEC University: co-supervised +13 Master's and 4 Doctor theses.
Professional Services
 Reviewer in Journals (past and present)
-IET journal of Circuits, Devices & Systems, Journal of Parallel and Distributed Computing, Integration: The VLSI Jnl, Journal of  Supercomputing

Conference/Program Committee Chair
  • Steering Committee Chair, IEEE 6th International Symposium on Embedded Multicore SoCs,The University of Aizu, Aizu-Wakamatsu, Japan, September 20-22, 2012.
  • Session Chair, IEEE Symposium on Low-power and High-speed Chips (COOL Chips XI), Yokohama, April 18-20, 2012
  • Program co-chair, 5th International Workshop of Engineering Parallel and Multicore Systems, July 4-6, 2012, Palermo, Italy.
  • Area Chair of the Parallel, Distributed and Multicore Computing track,  IEEE 14-th International Conference on Network-Based Information Systems (NBiS-2011).
  • Session Chair, 39th International Conference on Parallel Processing (ICPP2010), San Diego, Sept. 13-16, 2010.
  • Steering Committee Chair, 5th International Symposium on Embedded Multicore Systems-on-chip (MCSoC-10), San Diego, Sept. 13-16, 2010,
  • Area Chair of Distributed Algorithms and Systems track, 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Fukuoka, Nov. 4-6, 2010.
  • Area Chair of Parallel and Distributed Algorithms track, 13th International Conference on Network-Based Information Systems, Takayama, Sep. 14-16, 2010.
  • Steering Committee Chair, 4th International Symposium on Embedded Multicore Systems-on-chip (MCSoC-09), Vienna,  2009
  • Publication Chair, 4th International Conference on Frontier of Computer Science and Technology (FCST2009), Shanghai, 2009.
  • Program Chair, IEEE International Conference on Embedded Software and Systems, HangZhou, Zhejiang, China, 2009.
  • Publicity Chair, IEEE International Conference on Embedded and Ubiquitous Computing, (EUC2008), Shanghai, China, 2008.
  • General Chair, 3rd International Workshop on Embedded Single and Multicore Systems on Chips, In conjunction with 36th ICPP-2007, China, 2007
  • Steering Committee Chair, 2nd International Workshop on SoC and MCSoC Design with MoMM 2006,  Yogyakarta, Indonesia, 2006.
  • Program Co-chair, 3rd International Workshop on Embedded Computing with ICPP-06, Ohio, USA, 2006.
  • General Co-chair, 8th International Workshop on High Performance Scientific and Engineering Computing, USA, 2006.
  • Program Co-chair,  International conference on computer design, CDES-05, Las Vegas, 2005.
  • Session Chair, 5th International Conference on Embedded And Ubiquitous Computing (EUC2005), Nagasaki, Japan, 2005.
  • Organizing Chair,  Joint Workshop on Computer Systems and Information Technology, The University of Electro-communications (JT-CSIT2004),Tokyo, Japan, 2004.
Links
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Updated on 01.04.2012