MCSoC-09
in conjunction with
4th International Symposium on Embedded Multicore Systems-on-Chip
In conjunction with the
38th International Conference on Parallel Processing (ICPP 2009)
September 22-25, 2009, Vienna, Austria
Author kit |
Accepted paper list  |
Final Program |
Venue and Hotel |
|
|
|
|
|
Previous events
|
| MCSoC-07 |
| SoC-06 |
| SoC-05 |
|
|
MCSoC-09 Accepted papers list
Topology Generation CAD Tool for Multi-core Embedded System on
a Chip
Gul Khan and Victor Dumitriu
E-mail: gnkhan@ee.ryerson.ca
Towards a Component-based Observation of MPSoC
Carlos Hernan Prada Rojas, Vania Marangozova-Martin, Kiril
Georgiev,
Jean-François Méhaut and Miguel Santana
E-mail: Carlos-Hernan.Prada-Rojas@imag.fr
The Rendezvous Mechanism for the Multi-Core AMBA System
Jih-Ching Chiu, Kai-Ming Yang and Mu-Chi Chang
E-mail: hiujihc@ee.nsysu.edu.tw, d953010024@gmail.com
Structural Locality aware Analysis of Triplet based Interconnection
Strategy for Multi-Core On-Chip Processors
Haroon-Ur-Rashid Khan
E-mail: haroon65@gmail.com
A heuristic (Delta, D) digraph to interpolate between Hypercube and De
Bruijn topologies for future on chip interconnection networks
Samer Damaj, Thierry Goubier, Frederic Blanc and Bernard
Pottier
E-mail: srdamaj@hotmail.com
Balanced Dimension Order Routing for k-ary n-cubes
Jose Miguel Montañana Aliaga, Michihiro Koibuchi,
Hiroki
Matsutani and Hideharu Amano
E-mail: jmontana@nii.ac.jp, koibuchi@nii.ac.jp
Evaluation of d-mesh Interconnect for SoC
Roman Trobec
E-mail: roman.trobec@ijs.si
Resource Sharing in Networks-on-Chip of large many-core Embedded Systems
Fadi Sibai
E-mail: coti3@hotmail.com
Supporting Multitasking of Pipelined Computations on Embedded Parallel
Processor Arrays
Dimitris Syrivelis and Spyros Lalis
E-mail: dimitris.syrivelis@gmail.com , lalis@inf.uth.gr
An Accurate and Energy Efficient Fetch Direction Orientation Mechanism
for Trace Cache
Deze Zeng, Minyi Guo, Xin Liu, Song Guo and Hai Jin
E-mail: dazzae@gmail.com
Vahid Lari, Frank Hannig and Jürgen Teich
E-mail: Vahid.lari@informatik.uni-erlangen.de
Runtime Adaptation in Reconfigurable System-on-Chips
Abdel Ejnioui
E-mail: aejnioui@poly.usf.edu
Dynamic Way Prediction Technique for Low-Power Shared L2 Caches
Chun-Mok Chung and Jihong Kim
E-mail: chunmok@davinci.snu.ac.kr, jihong@davinci.snu.ac.kr
Gating and Serializing the Data Path of CPU for Low Power Consumption
Rajesh Kannan Megalingam, Venkat Krishnan B, Rahul Srikumar, Mithun M and Vineeth Sarma
E-mail: venkatkrishnan.b@gmail.com, raven_dragoon75@yahoo.co.in, mithun34@ieee.org, vineethisalways4u@gmail.com
Software and Hardware Design Issues for Low Complexity High Performance Embedded Processor
Masashi Masuda , Abderazek Ben Abdallah
E-mail: m5131145@u-aizu.ac.jp , benab@u-aizu.ac.jp
Phased Set Associative Cache Design For Reduced Power Consumption
Rajesh Kannan Megalingam, Deepu K B, Iype Joseph and Vandana Vikram
E-mail: rajeshm@amritapuri.amrita.edu