AIzuHand:
Adaptive
Real-time
Non-invasive
Neuromorphic
Prosthesis
Hand
Prosthetic
limbs can
significantly
improve the
quality of
life of people
with
amputations or
neurological
disabilities.
With the rapid
evolution of
sensors and
mechatronic
technology,
these devices
are becoming
widespread
therapeutic
solutions.
However,
unlike living
agents that
combine
different
sensory inputs
to perform a
complex task
accurately,
most
prosthetic
limbs use
uni-sensory
input, which
affects their
accuracy and
usability.
Moreover, the
methods used
to control
current
prosthetic
limbs (i.e.,
arms and legs)
generally rely
on sequential
control and
power-hungry
strategies
with limited
natural motion
and long and
complicated
training
procedures.
This
project is
about the
development of
an advanced
real-time
neuromorphic
prosthesis
hand,
AIzuHand, with
sensory
integration
and feedback
sensing. In
addition, we
investigate a
user-friendly
software tool
for
calibration,
real-time
feedback, and
functional
tasks.
NASH:
3D Spiking
Neuromorphic
Processor
This
project aims
to research
and develop an
adaptive
low-power
spiking neural
network system
in hardware
(NASH)
empowered with
our earlier
developed
fault-tolerant
three-dimensional
on-chip
interconnect
technology.
The NASH
system
features the
followings:
(1) an
efficient
adaptive
configuration
method that
enables
reconfiguration
of different
SNN parameters
(spike
weights,
routing,
hidden layers,
topology,
etc.), (2) a
mixture of
different deep
NN topologies,
(3) an
efficient
fault-tolerant
multicast
spike routing
algorithm, (4)
Efficient
on-chip
learning
mechanism. To
demonstrate
the
performance of
NASH system,
an FPGA
implementation
shall be
developed,
and VLSI
implementation
shall also be
established.
AIRBiS:
Reconfigurable
AI-Enabled
System for
Pneumonia
Detection
The
success of
deep learning
in extending
the frontiers
of artificial
intelligence
has
accelerated
the
application of
AI-enabled
systems in
addressing
various
challenges in
different
fields. In health
care, deep
learning is
deployed on
edge computing
platforms to
address
security and
latency
challenges,
even though
these
platforms are
often
resource-constrained.
Deep learning
systems are
based on
conventional
artificial
neural
networks,
which are
computationally
complex,
require high
power, and
have low
energy
efficiency,
making them
unsuitable for
edge computing
platforms.
Since these
systems are
also used in
critical
applications
such as
bio-medicine,
it is
expedient that
their
reliability is
considered when
designing
them. For
biomedical
applications,
the
spatio-temporal
nature of
information
processing of
spiking neural
networks could
be merged with
a
fault-tolerant
3-dimensional
network
on chip
(3D-NoC)
hardware to
obtain an
excellent
multi-objective
performance
accuracy while
maintaining
low latency
and low power
consumption.
This
project
investigates
an AI-Powered
hardware-software
co-design for
pneumonia
detection. The
system is
based on a
high-performance,
low-power
re-configurable
inference
AI-chip, a
robust
collaborative-learning
mechanism for
privacy-preserving,
and a
real-time
interactive
interface for
effective
operation and
monitoring.
AEBiS:
AI-Enabled
Off-Grid
Energy Storage
Solar Carport
A
Virtual Power
Plant (VPP) is
a network of
distributed
power
generating
units,
flexible power
consumers, and
storage
systems. A VPP
ba lances
the load on
the grid by
allocating the
power
generated by
different
linked units
during periods
of peak load.
Demand-side
energy
equipment,
such as
Electric
Vehicles (EVs)
and mobile
robots, can
also balance
the energy
supply-demand
when
effectively
deployed.
However,
fluctuation of
the power
generated by
the various
power units
makes the
supply power
balance a
challenging
goal. Mor
eover,
the
communication
security
between a
VPP aggregator
and end facilities
is critical
and has not
been carefully
investigated.
In
this project,
we collaborate
with
Aizu Computer
Science
Laboratories,
Inc. and Banpu
Japan to
develop an
AI-enabled,
blockchain-based
electric
vehicle
integration
system for
power
management in
a smart grid
platform based
on EV and
solar carport.
We have
developed
a
low-power
AI-chip and
various
software tools
for EV charge
prediction, in
which the EV
fleet is
employed as a
consumer and
as a supplier
of electrical
energy.
PHENIC:
Fault-resilient
Si-Photonics
Network-on-Chip
The
large
computing
power of
multi-processor
systems would
require very
large on-chip
and off-chip
data transfer
rates (>
100TB/s). One
efficient
technology for
transmitting
this level of
information is
the photonics
interconnects,
which promise
significant
advantages
over their e lectronic
counterparts.
In particular,
nanophotonics
(light on the
nanometer
scale on
nanometer-scale
devices)
on-chip
interconnects
offer a
potentially
disruptive
technology
solution with
fundamentally
low power
dissipation,
ultra-high
bandwidth, and
low latency.
Also, when
combined with
3D integration
technology,
photonics
interconnect
offers
advantages
over
electronic 2D
NoC design,
such as
shorter wire
length, higher
packing
density, and
smaller
footprint.
Moreover, to
ensure that
these complex
systems can
accommodate
faults and
maintain
operation,
there is a
need for the
development of
an efficient
mechanism that
can
self-detect,
self-diagnosis
and
self-recover
in the
processing
cores as well
as in the
on-chip
interconnect
(NOC). The
goal of this
project is to
study novel
photonic
interconnect
solutions to
improve energy
efficiency,
and bandwidth
of on-chip
interconnects
for embedded
and
high-performance
many-core
systems. The
aging
typically
occurs faster
inactive
components as
well as
elements that
have high
thermal
variation. In
the optical
domain, faults
can occur in
MRs, waveguides,
routers, etc.
Active
components,
such as
photodetectors,
have
higher failure
rates than
passive
components,
e.g.
waveguides.
Moreover, when
paired
with the
fact that a
PNoC is highly
vulnerable, as
a fault may
expose the
single-point failure,
a faulty MR
can cause a
message to
misdelivered
or lost.
OASIS:
Fault-tolerant
3D-TSV-based
Network-on-Chip
Future
System-o
n-Chip
(SoC) will
contain
hundreds of
components
made of
processor
cores, DSPs,
memory,
accelerators,
and I/O all
intergared
into a single
die area of
jus t
a few square
millimeters.
Such complex
system/SoC
will be
interconnected
via a novel
on-chip
interconnect
closer to a
sophisticated
network than
to current
bus-based
solutions.This
network must
provide high
throughput and
low latency
while keeping
area and power
consumption
low.
Our research
effort is
about solving
several design
challenges to
enable such
new paradigm
in massively
parallel
many-core
systems. In
particular, we
are
investigating
fault-tolerance,
3D-TSV
integration,
photonic
communication,
low-power
mapping
techniques,
low-latency
adaptive
routing.
QCore:
Queue
Processor
Architecture
and Design
(1999-2008)
This project
is about the
research and
design of a
low-power
Queue
processor
architecture
based on a
Queue
computation
model, where a
queue
program is
generated by
traversing a
data flow
graph using
level-order-traversal
scheme. The
Queue
processor uses
a circular
queue register
to manipulates
operands and
results and
exploits
parallelism
dynamically
with
“little efforts”
when compared
with
conventional
architectures.
The
nonexistence
of false
dependencies
allows
programs to
expose maximum
parallelism
that the queue
processor can
execute
without
complex and
power-hungry
hardware such
as register
renaming and
large
instruction
windows. Parallel
processing
allows queue
processors to
speed-up the
execution of
applications.
We are
researching
and developing
a complete
tool-chain for
this
non-conventional
computing
paradigm,
including a Q
compiler,
assembler,
cycle accurate
simulator, and
a hardware
prototype on
FPGA and ASIC.
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