Adaptive Systems Laboratory


RESEARCH



AY2019 MEMBERS



ALUMNI

  1. Vu Huy The, ''Algorithms and Architectures for Spiking Neuromorphic Systems,'' Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 9/2019
  2. Ryunosuke Murakami, ''Animal Recognition and Identification with Convolutional Neural Networks for Farm Monitoring,'' Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 9/2019
  3. Yuji Murakami, '' Design of a Neural Network Architecture for Traffic Light Detection Towards Autonomous Driving Vehicles,'' Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 3/2019
  4. Akihito Kajikawa,''Performance and Complexity Study of  Network-on-Chip with Custom Topology on FPGA,'' 'Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 3/2019
  5. Shinji Hironaka, ''Design and Evaluation of a Clustered LIF Neuro-Core for Spiking Neural Network (NASH),'' Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, 3/2019
  6. Yoshiki Tanaka, 'Performance Study of Kanji Recognition with Feed-Forward Neural Network Architecture,'' Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, 3/2019
  7. Nam Khanh Dang, ”Development of On-Chip Communication Fault-Resilient Adaptive Architectures and Algorithms for 3D-IC Technologies”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 9/2017. 
  8. Michael Meyer, ”Micro-ring Fault-resilient Photonic On-chip Network for Reliable High-performance Many-core Systems-on-Chip”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 3/2017.
  9. Achraf Ben Ahmed, ''High-performance, Scalable Photonics On-chip Network for Many-core Systems-on-Chip'', Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 3/2016.
  10. Akram Ben Ahmed, ''High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems'', Ph.D. Thesis, Graduate School of Computer Science and Engineering, University of Aizu, 3/2015.
  11. Masaki Yamada, ”Performance Study of Character Recognition with Feed-Forward Neural Network”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
  12. Kanta Suzuki ”Design of a Leaky, Integrate and Fire (LIF) Neuron Core for NASH System”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
  13. Kosuke Takakuwa, ”Study of a Neuro-inspired Architecture in Hardware”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
  14. Yuji Murakami, “Design of a Light-Weight Control Network for High-Bandwidth Photonic Network-on-Chip Systems”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017.
  15. Nao Miyamoto, “Video Classification with Numbers of Detected Trajectories Using Time-space Continuous Dynamic Programming”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017.
  16. Kaori Yatsu, “Visualization of Educational Processor in UML”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017.
  17. Kajikawa, Akihito, Evaluation of Error Detection Mechanism for 3D-OASIS-Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.
  18. Saito, Ken, Design, and Analysis of Electrical Control Router for Hybrid Photonics NoC System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.
  19. Okada, Ryoga, Power and Performance Comparison of Electronic 2D-NoC and Opto-Electronic 2D-NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.
  20. Mitsunari Ishii, Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015.
  21. Yuuki Tanaka, Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015.
  22. Yumiko Kimezawa, Towards the Design of Dependable Real-Time System for Remote Health Monitoring of Elderly People, Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
  23. Achraf Ben Ahmed, Interactive Real-time Interface for Smart Remote Health Monitoring and Analysis, Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
  24. Takayuki Ochi, A Quantitative Performance Study of Shared Memory Multicore Systems, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
  25. Shuu Endou, Hardware Prototyping and Evaluation of Distributed Routing Core Network-Interface for OASIS NoC Architecture, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
  26. Kenichi Mori, OASIS Network-on-Chip Prototyping on FPGA, Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012.
  27. Akram Ben Ahmed, Architecture and Design of 3D Network-on-Chip, Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012
  28. Shohei Miura, Design of Parametrizable Network-on-Chip, Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012.
  29. Ryuya Okada, Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2012.
  30. Tomotaka Kasahara, Performance and Complexity Study of Multi-QueueCore Systems, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2012.
  31. Hiroki Hoshino, Development of Parallel Queue Processor Architecture and its Integrated Development Environment, Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
  32. Taichi Maekawa, Design and Evaluation of Dual Mode Processor Architecture, Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
  33. Masashi Masuda, Produced Order Queue Compiler Design, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
  34. Takahiro Uesaka, OASIS NoC Topology Optimization with Short Path Link, Bachelor Thesis, School of Computer Science and Engineering, the University of Aizu, Feb. 2011.
  35. Shunichi Kato, Shared Memory MultiQueueCore Processor Design, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011, Ref. 10SK-GT10.
  36. Yumiko Kimezawa, Multicore SoC Architecture for Real-time Data Intensive ECG Processing, Bachelor Thesis, School of Computer Science and Engineering, the University of Aizu, Feb. 2011.
  37. Yuuki Omoto, Development Environment for Single Chip Computer intended for Queue Computing Development and Education, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010.
  38. Haga Yasuyoshi, Architecture and Design of Application Specific Multicore SoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010.
  39. Reo Honjoya, Development of User-Friendly Assembler for Queue Computers, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010.
  40. Mori Kenichi, Optimizations Techniques and FPGA Prototyping of OASIS Network-on-Chip, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010.
  41. Miura Shohei, Architecture and Design of Parameterizable Network-on-Chip, Bachelor Thesis, School of Computer Science and Engineering, the University of Aizu, Feb. 2010.
  42. Masashi Masuda, Graph Transformation Methods and Theoretical Performance Evaluation of Queue Computation Models, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
  43. Hiroki Hoshino, Advanced Hardware Optimization Algorithms for High-Performance Queue Processor Architecture, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
  44. Tachi Maekawa, Research on Hardware Design of Dual-Mode Processor Architecture, Bachelor Thesis, School of Computer Science and Engineering, the University of Aizu, Feb. 2009.

Last update: 3/19/2018