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2019”N3ŒŽ CŽm‘²
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Layout Design Method for Low Power in General-synchronous Framework Using Multiple Supply Voltages
2019”N3ŒŽ Šw•”‘²
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Power Consumption Reduction of Arduino Compatible Board by DVFS
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FPGA Implementation of AVR Compatible Processor in General-Synchronous Framework
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Maximum Wire Length Routing Algorithm by Upper Bound Estimation on PCB
2018”N3ŒŽ CŽm‘²
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Analytical Pacement Using SPICE Simulator in LSI Circuits
2018”N3ŒŽ Šw•”‘²
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Pixel-based OPC using Quadratic Programming for Mask Optimization
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Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning
Š±ź Ž÷
Acceleration of Analytical Placement by Wire Length Prediction using Machine Learning
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Implementation of AVR Compatible Processor into FPGA in General-Synchronous Framework
2017”N3ŒŽ ”ŽŽm‘²
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Digital LSI Design Methods Considering Process Variations in Advanced Technology Nodes
2017”N3ŒŽ CŽm‘²
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Implementation Flow in General-Synchronous Framework using Engineering Change Order for Xilinx FPGA
2017”N3ŒŽ Šw•”‘²
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Design Method using Multiple Supply Voltages for Low Power in General-Synchronous Framework
2016”N3ŒŽ CŽm‘²
‘åź ‘ō–ē
Implementation of General-synchronous Circuits into Altera FPGA using Prescribed-Domain Clock Skew Scheduling
2016”N3ŒŽ Šw•”‘²
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Analytical Placement Using SPICE Simulator in LSI Circuits
2015”N3ŒŽ CŽm‘²
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Acceleration for Any-Angle Routing using Quasi-Newton Method on GPGPU
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Technology Mapping Method for Low Power Consumption in General-Synchronous Framework
2015”N3ŒŽ Šw•”‘²
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Iterative Improvement Method for Peak Power Reduction using Multi-Clustering Method in General-Synchronous Framework
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Improvement of Design Flow for FPGA Implementation in General-synchronous Framework
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Enhancement of Routing Method using Quasi-Newton Method
2014”N3ŒŽ CŽm‘²
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Analytical Placement using Quasi-Newton Method and Acceleration by GPGPU
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A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement
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Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling
2014”N3ŒŽ Šw•”‘²
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Double Patterning Lithography Layout Decomposition Considering Balance
‘O“c —Eģ
Iterative Improvement Method for Peak Power Reduction using 2-clustering in General-Synchronous Framework
‘åź ‘ō–ē
Layout Design of General-Synchronous Circuits by Current CAD Tools
2013”N3ŒŽ Šw•”‘²
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Technology Mapping for Low Power Consumption in General-Synchronous Framework
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Peak Power Reduction using 2-Clustering Method in General-Synchronous Framework
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A Study of Longest Path Problem for a Differential Pair Net
2012”N3ŒŽ Šw•”‘²
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An Effective Overlap Removable Objective for Analytical Placement
ŒĆŽR Ė•½
A Length-Matching Routing Algorithm on Single Layer using Longer Path Algorithm for Single Net
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Acceleration of Parallel Maze-Routing Algorithm Using GPGPU
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Timing Recovery Method for LSI Circuits with Programmable Delay Element