AIzuHand: Adaptive Real-time Non-​invasive Neuromorphic Neuroprosthesis Hand

Prostheses/Neuro-prostheses can significantly improve the quality of life of people with neurological disabilities. These devices are becoming widespread therapeutic solutions (i.e., Parkinson's disease, retinal implants, walking rehabilitation, restoration of sensory feedback in limb prostheses, breast engorgement or palpation, etc.).  However, unlike living agents that combine different sensory inputs to perform a complex task accurately, most prosthetics and anthropomorphic robotics arms use uni-sensory input, which affects their accuracy. Yet, they are power-hungry devices due to their controlling methods. Therefore, understanding the richness of the sensorimotor functions of the prosthesis hand and their adaptivity remains one of the challenges in modern science and engineering. This project investigates an advanced real-time and power-efficient neuromorphic prosthesis hand, AIzuHand, with sensorimotor integration and feedback sensing. We aim to develop solutions for controlling prosthetic limbs to restore movement to people with neurologic impairment and amputation..

NASH: Event-Driven Low-power 3D Digital Spiking Neuromorphic System with On-line Learning

This project aims to research and develop an adaptive low-power spiking neural network system in hardware (NASH) empowered with our earlier developed fault-tolerant three-dimensional on-chip interconnect technology. The NASH system features the followings: (1) an efficient adaptive configuration method that enables reconfiguration of different SNN parameters (spike weights, routing, hidden layers, topology, etc.), (2) a mixture of different deep NN topologies, (3) an efficient fault-tolerant multicast spike routing algorithm, (4) Efficient on-chip learning mechanism. To demonstrate the performance of NASH system, an FPGA implementation shall be developed, and  VLSI implementation shall also be established.

AEBiS: Smart and Secure Energy Trading Method and System

A Virtual Power Plant (VPP) is a network of distributed power generating units, flexible power consumers, and storage systems. A VPP balances the load on the grid by allocating the power generated by different linked units during periods of peak load.
Demand-side energy equipment, such as Electric Vehicles (EVs) and mobile robots, can also balance the energy supply-demand when effectively deployed. However, fluctuation of the power generated by the various power units makes the supply power balance a challenging goal. Moreover, the communication security between a VPP aggregator and end facilities is critical and has not been carefully investigated.
In this project, we collaborate with  Aizu Computer Science Laboratories, Inc. and Banpu Japan to develop an AI-enabled, blockchain-based electric vehicle integration system for power management in a smart grid platform based on EV and solar carport. We have developed a  low-power AI-chip and various software tools for EV charge prediction, in which the EV fleet is employed as a consumer and as a supplier of electrical energy.

AIRBiS: AI-Powered Hardware-Software Platform Co-Design for Pneumonia Detection

The success of deep learning in extending the frontiers of artificial intelligence has accelerated the application of AI-enabled systems in addressing various challenges in different fields. In health care, deep learning is deployed on edge computing platforms to address security and latency challenges, even though these platforms are often resource-constrained.  Deep learning systems are based on conventional artificial neural networks, which are computationally complex, require high power, and have low energy efficiency, making them unsuitable for edge computing platforms. Since these systems are also used in critical applications such as bio-medicine, it is expedient that their reliability is considered when designing them.
For biomedical applications, the spatio-temporal nature of information processing of spiking neural networks could be merged with a fault-tolerant 3-dimensional n
etwork on chip (3D-NoC) hardware to obtain an excellent multi-objective performance accuracy while maintaining low latency and low power consumption.
This project investigates an AI-Powered hardware-software co-design for pneumonia detection. The system is based on a high-performance, low-power re-configurable inference AI-chip, a robust collaborative-learning mechanism for privacy-preserving, and a real-time interactive interface for effective operation and monitoring.

PHENIC: Fault-resilient Si-Photonics Network-on-Chip for Reliable Many-core Systems-on-Chip

The large computing power of multi-processor systems would require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the photonics interconnects, which promise significant advantages over their electronic counterparts. In particular, nanophotonics (light on the nanometer scale on nanometer-scale devices) on-chip interconnects offer a potentially disruptive technology solution with fundamentally low power dissipation, ultra-high bandwidth, and low latency. Also, when combined with 3D integration technology, photonics interconnect offers advantages over electronic 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. Moreover, to ensure that these complex systems can accommodate faults and maintain operation, there is a need for the development of an efficient mechanism that can self-detect, self-diagnosis and self-recover in the processing cores as well as in the on-chip interconnect (NOC). The goal of this project is to study novel photonic interconnect solutions to improve energy efficiency, and bandwidth of on-chip interconnects for embedded and high-performance many-core systems. The aging typically occurs faster inactive components as well as elements that have high thermal variation. In the optical domain, faults can occur in MRs, waveguides, routers, etc. Active components, such as photodetectors, have higher failure rates than passive components, e.g. waveguides. Moreover, when paired with the fact that a PNoC is highly vulnerable, as a fault may expose the single-point failure, a faulty MR can cause a message to misdelivered or lost.

OASIS: Development of Fault-tolerant High-performance On-Chip Communication Network for Embedded Multicore SoCs

Future System-on-Chip (SoC) will contain hundreds of components made of processor cores, DSPs, memory, accelerators, and I/O all intergared into a single die area of just a few square millimeters. Such complex system/SoC will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions.This network must provide high throughput and low latency while keeping area and power consumption low.
Our research effort is about solving several design challenges to enable such new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, low-latency adaptive routing.

BANSMOM: Dependable Real-Time Multicore System-on-Chip for Elderly Health Monitoring

Recent technological advances in wireless n to change fundamentally the way elderly health care services are practiced. Traditionally, embedded personal medical monitoring systems have been used only to collect data. Data processing and analysis are performed off-line, making such devices impractical for continual monitoring and early detection of medical disorders. The goal of this project is to research a smart, dependable embedded system to monitor elderly health remotely and in real-time. In particular, we investigate an extreme area in the design space of networked embedded objects: the domain of low energy, and real-time. Issues related to the design, implementation, and deployment of such systems are also studied.

QCore: Research and Development of a Low-power Queue Processor
This project is about the research and design of a low-power Queue processor architecture based on a so called Queue Computation Model (QCM), where a queue  program is generated by traversing a data flow graph using level-order-traversal scheme. The Queue processor uses a circular queue register to manipulates operands and results and exploits parallelism dynamically with “little efforts” when compared with conventional architectures. The nonexistence of false dependencies allows programs to expose maximum parallelism that the queue processor can execute without complex and power-hungry hardware such as register renaming and large instruction windows. Parallel processing allows queue processors to speed-up the execution of applications. We are researching and developing a complete tool-chain for this promising computing model consisting of a compiler, assembler, functional and cycle accurate simulator, and hardware design.