Our research covers the following:
  • Neuromorphic computing; Spike-based learning and neural system dynamics
  • Motor control and adaptive learning mechanism
  • Fault-tolerance and reliability
  • High-speed, Low-power on-chip interconnection networks; Embedded SoCs
  • Development of advanced adaptive neuromorphic prostheses & anthropomorphic robotics technology

  • Adaptive Real-time Neuromorphic Non-invasive Prostheses and Anthropomorphic Robotics
    The use of robot limbs in various fields of human endeavor has increased over the years. Moreover, recent advancements in deep learning and assistive robots are increasingly being employed in many applications. However, unlike living agents that combine different sensory inputs to perform a complex task accurately, most prosthetic/robot limbs use uni-sensory input, which affects their accuracy and usability. Therefore, understanding the richness of sensorimotor functions remains one of the challenges in modern science and engineering. Based on sensorimotor integration, neuromorphic circuits and systems, and 3D printing technology, we investigate advanced neuromorphic non-invasive prostheses and anthropomorphic robots - where reliability and real-time criteria are critical. Furthermore, we aim to develop solutions for controlling prosthetic limbs to restore movement to people with neurologic impairment and amputation. Application of this research effort range from simple prosthetic limbs to advanced surgical operations, unmanned exploration, and assistive/welfare anthropomorphic robots.  

  • Ultra Low-power Event-Driven Brain-inspired Computing Systems
    We study adaptive, ultra-low-power spiking neural network processors and systems in hardware based on our earlier developed 2D/3D communication networks. The neuromorphic (NASH) system implements efficient adaptive configuration method (spike weights, routing, hidden layers, topology, etc.), a mixture of different network topologies, and efficient on-chip learning mechanism. To demonstrate the performance of NASH system, an FPGA implementation shall be developed, and VLSI implementation shall also be established.

  • Computing with Spiking Neural Networks
    We aim to understand the role of spike-based learning in brain-inspired systems by considering various constraints that are not usually taken into account in simulations, such as the effect of variability in the neural network parameters or the impact of bounded weights in the learning/training phase. We study how a cluster of spiking neurons computes and communicates information with different learning and plasticity mechanisms such as short-term or long-term potentiation. We also explore how these networks can be realized efficiently on silicon.
  • Low-power, high-speed on-chip interconnection networks for Single and Mulicore SoCs
    Complex SoCs contain dozens of components made of processor cores, DSPs, memory, accelerators, and I/O all integrated into a single die area of just a few square millimeters. Such complex systems will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions.This network must provide high throughput and low latency while keeping area and power consumption low.
    Our research effort is about solving several design challenges to enable such new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, low-latency adaptive routing.

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