AY 2026 Undergraduate School Course Catalog AY 2026 Undergraduate School Course Catalog AY 2026 Undergraduate School Course Catalog
| 2026/02/19 |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
4.0 |
| 責任者 ／Coordinator |
SUZUKI Daisuke |
| 担当教員名 ／Instructor |
HISADA Yasuhiro, SUZUKI Daisuke |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
Courses preferred to be learned prior to this course (This course assumes understanding of entire or partial content of the following courses) LI13 CSE Exercise I, NS04 Semiconductor Devices |
| 更新日／Last updated on | 2026/02/06 |
|---|---|
| 授業の概要 ／Course outline |
Because CMOS technologies are widely used in modern electronics such as cellular and smart phones, we need advanced knowledge of CMOS circuits. Moreover, recently the demand for mixed-signal CMOS LSIs, including analog and RF (Radio Frequency) circuits, is very rapidly increasing, especially for consumer electronics and communication equipment. This course covers basic CMOS analog circuits design. First, basics of VLSIs and electrical circuits including transient analysis will be reviewed. Then, the load line analysis will be introduced and will be applied to basic MOS amplifiers. From the AC performance analysis, small signal equivalent circuits will be given. Finally, OP amplifier and basics of A/D & D/A converters will be covered. A hands-on approach is emphasized through laboratory exercises in which the student develops skills using the basic test equipment. Starting from series LC resonant circuits, parallel LC resonant circuits will be covered. Then, MOSFET amplifiers with resistive loads will be covered. The student can also learn close relationship between analog amplifiers and digital inverters observing pulse responses of the MOSFET amplifier. Finally, basic Op amplifier circuits and a low-bit A/D converter will be covered. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
[Corresponding Learning Outcomes] (A)Graduates are aware of their professional and ethical responsibilities as an engineer, and are able to analyze societal requirements, and set, solve, and evaluate technical problems using information science technologies in society. [Competency Codes] C-AR-006 The primary goals of this course are: 1. To familiarize the student with the basic laws and theorems used in the analysis of electrical and electronic circuits and in the computation of circuit values. 2. To develop the student’s ability to analyze, construct and test electric and electronic circuits connected in various configurations. 3. To deepen understanding of students on CMOS analog and digital circuits as the mainstream VLSI technology. Students will be able to: 1. Create a small signal equivalent circuit of a given CMOS analog circuit. 2. Analyze circuit performances such as voltage gain and frequency responses. 8. Understand mechanism of A/D & D/A converters. |
| 授業スケジュール ／Class schedule |
[Course Content and Format] Lectures and experiments will be conducted on separate days (to be announced separately); for example, lectures on Tuesdays and experiments on Fridays. Lectures will be held a total of 7 times, with each session consisting of four 50-minute periods. Each session will include explanations of the topic and related practice problems, which students are expected to solve individually and submit on their own. Lecture Topics: 1. Review of basic electrical circuits (Thevenin and Norton equivalents, parallel LC circuit) 2. Transient analysis (RC, LRC circuits), Review of semiconductor devices. 3. Bipolar transistor basics, MOSFET basics: DC current, load line analysis, small signal (AC) model, parasitic capacitances of MOSFET, Miller effect. 4. Basic MOS amplifiers (common source, common drain, common gate), frequency responses, MOS composite circuits (active-load amplifier, cascode amplifier, CMOS amplifier). 5. Current mirror, differential amplifier, power amplifiers. 6. OP amplifier and its application circuits. 7. Sampling theorem, sample/hold circuit, basics of A/D & D/A converters. Experiments will also be conducted a total of 7 times, with each session consisting of four 50-minute periods. In principle, students will work in pairs for measurements and data processing, but each student must write and submit their own report. Experiment Topics: 1. LC-resonant circuits and in-depth experiments, sinusoidal-wave extraction from pulse waves using LC resonant circuits (Verifying the Fourier series). 2. Measuring MOSFET I-V curves and DC-transfer-function curves of an MOSFET amplifier using a resistive load (1). 3. Measuring MOSFET I-V curves and DC-transfer-function curves of an MOSFET amplifier using a resistive load (2). 4. Measuring gains and AC-transfer-function curves of an MOSFET amplifier using a resistive load. 5. Measuring gains and AC-transfer-function curves of a CMOSFET amplifier: Understanding close relationship between analog amplifiers and digital inverters. 6. OP amplifier applications: Inverting and non-inverting amplifiers 7. Low-bit A/D converter ② Pre-Class and Post-Class Study [Pre-Class Study] Handouts for both lectures and experiments will be available in advance via LMS. Students are expected to read the handouts and textbook before class, and identify what they understand and what they do not (approx. 1.5 hours). For experiments, students should also understand the purpose, content, and procedures in advance—what circuits will be built, how to operate the instruments, and what measurements will be taken (approx. 1.5 hours). [Post-Class Study] For lectures, students should review the handouts and textbook covered each week to deepen their understanding. Particularly for content not understood during pre-study, students should revisit it using the in-class explanation. If practice problems are not completed during class, they must be submitted by the end of the day. Students should refer to the model answers provided in later classes or on LMS to self-check their work and reattempt any incorrect parts to ensure understanding (approx. 4 hours). For experiments, students must organize their results and compile them into a report. If there are issues with the results and a re-experiment is necessary, students should consult with the instructor. Re-experiments may be allowed in the next class, outside class hours, or may not be permitted depending on the situation (approx. 10 hours). |
| 教科書 ／Textbook(s) |
松澤 昭、「はじめてのアナログ電子回路」（基本回路編）、講談社、ISBN978-4-06-156535-7 |
| 成績評価の方法・基準 ／Grading method/criteria |
Lecture: Terminal Exam (50%) Quizzes (10%) Experiment: Reports (40%) Note: If a student does not submit quizzes and experiment reports, his or her attendance cannot be approved. |
| 履修上の留意点 ／Note for course registration |
Related courses: Semiconductor Devices, CSE Exercise I, Fourier Analysis, Fourier Analysis |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
[Electric circuits] 1. Schaum's Outline of Electric Circuits, ISBN: 0071393072 2. 安居院、吉村、倉持、「エッセンシャル電気回路」 第2版、森北出版、ISBN978-4-627-73562-0 [Electronic circuits and MOS analog integrated circuits] 3. 松澤 昭、「はじめてのアナログ電子回路」（実用回路編）、講談社、ISBN978-4-06-156545-6 A/D・D/A変換器、アクティブ・フィルタなど 4. 谷口 研二、「CMOSアナログ回路入門」、CQ出版、ISBN4-7898-3037-3 5. B. Razavi、「アナログCMOS集積回路の設計 基礎編」、丸善、ISBN4-621-07220-X B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, ISBN-13: 978-0070529038 |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 4学期 ／Fourth Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
4.0 |
| 責任者 ／Coordinator |
KITAMICHI Junji |
| 担当教員名 ／Instructor |
KITAMICHI Junji, OKUYAMA Yuichi |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
Courses preferred to be learned prior to this course (This course assumes understanding of entire or partial content of the following courses) FU05 Computer Architecture FU06 Operating Systems FU14 Intro. to Software Engineering PL02 C Programming The exercises are mainly programming using C language. We recommend that you bring any C language books you already have. |
| 更新日／Last updated on | 2026/02/04 |
|---|---|
| 授業の概要 ／Course outline |
This course provides students with experience in embedded systems design. The course introduces issues in upstream design in embedded system and RTOS for real-time systems. There are also weekly laboratory sessions on design of a microprocessor-based embedded system including one or more custom peripherals. The exercises provide hands-on experience in designing and implementing embedded systems using a microcontroller. Students develop programs in the C language, gradually extending system functionality while considering time management, task structuring, and interaction with peripheral devices. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
(A)Graduates are aware of their professional and ethical responsibilities as an engineer, and are able to analyze societal requirements, and set, solve, and evaluate technical problems using information science technologies in society. [Competency Codes] C-AR-015,C-AR-016,C-AR-017, To serve as a capstone design course to tie together the computer engineering curriculum via the design of a complete embedded system involving multiple communicating components. [Exercise] Through the exercises, students will be able to design, implement, and verify embedded software on actual hardware, and explain their design decisions and program behavior in a structured manner. |
| 授業スケジュール ／Class schedule |
[Lecture] 1. Introduction of this course 2. Embedded Computing 3. Instruction Sets 4. CPUs 5. CPUs and Computing Platforms 1 6. Computing Platforms 2 7. System Architecture, modeling and etc. 8. State Charts and Object oriented approach 9. RTOS 10. ITRON 11. Real Time Processes 12. Priority-based scheduling 13. Priority inversion and etc. 14. Schedulability and Test and etc. [Lecture : Pre-class Learning] The slides used in the lectures are uploaded to the LMS in advance. Read the slides in advance and sort out what you understand and what you don't. If you don't understand something, we recommend you look it up online and etc. [Lecture : Post-class Learning] For quizzes conducted during lectures, the answers or ways of thinking will be displayed in the file on the LMS, so check your answers and make sure you understand them. Review the contents of the lecture, especially the terminology, and make sure you understand and remember them. [Exercise] The exercises consist of Exercises 1-7, each conducted over two sessions (total 14 sessions). Each session is composed of 100 minutes of lecture and 100 minutes of exercise. 1-2. Exercise 1: Development environment setup and basic operation 3-4. Exercise 2: GPIO input and output and basic control 5-6. Exercise 3: Software-based time management and periodic processing 7-8. Exercise 4: I2C communication and LCD control 9-10. Exercise 5: Extension of periodic tasks and functional integration 11-12. Exercise 6: Advanced task design considering execution constraints 13-14. Exercise 7: Comprehensive exercise integrating previous components [Exercise : Pre-class Learning] Read the distributed PDF materials in advance, clarify unclear points, and identify where the information necessary for system design is described. Approx. 2 hours per two exercise sessions. [Exercise : Post-class Learning] If the program is not completed during class time, continue development after class. In addition, prepare an exercise report based on program behavior and design considerations. Approx. 4 hours per two exercise sessions. |
| 教科書 ／Textbook(s) |
Lecture materials are provided as handouts. The handouts summarize key points from the reference materials. Exercise materials are distributed via the LMS and UNIX directories. |
| 成績評価の方法・基準 ／Grading method/criteria |
Final examination (50%) and reports of exercises (50%). For the exercises, verification of correct hardware operation is mandatory for evaluation. Reports without confirmed operation will not be graded. Reports are evaluated based on the following criteria: - Operation verification - Design explanation - Code presentation - Discussion and analysis |
| 履修上の留意点 ／Note for course registration |
In the exercises, programming is performed using the C language. Microcontroller kits (Pico, IoT kit, LCD, cables, etc.) are provided. Borrowed equipment may be taken outside the classroom for use after class upon submission of a borrowing form. Collaboration is limited to discussion; sharing code or reports is not permitted. The use of generative AI tools is not allowed in exercises or reports. |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Materials for this course are available on ELMS in UoA. References are as follows. 1-6: Computers as Components, 4th Edition, Morgan Kaufmann 組込みシステム設計の基礎, 日経BPは, 上記の1st Editionの翻訳であり, 4thと内容が大きく異なるので注意) The following chapters are not covered. Chapter 8. Internet-of-Things Systems Chapter 9. Automotive and Aerospace Systems Chapter 10. Embedded Multiprocessors 7-14: 組み込みシステム開発に役立つ理論と手法 藤倉 俊幸, CQ出版, 絶版. 12 and 13: 組込みソフトウェア開発技術の基礎 Edited: NCES人材育成プログラム https://www.nces.i.nagoya-u.ac.jp/NEP/materials/about.html |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 3学期 ／Third Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
NAKASATO Naohito |
| 担当教員名 ／Instructor |
NAKASATO Naohito, BEN ABDALLAH Abderazek |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
Courses preferred to be learned prior to this course (This course assumes understanding of entire or partial content of the following courses) F5 Computer Architecture F6 Operationg System |
| 更新日／Last updated on | 2026/02/03 |
|---|---|
| 授業の概要 ／Course outline |
A large change in the computing world has started in the last decade: not only are the fastest computers parallel, but nearly all computers will soon be parallel, because the physics of semiconductor manufacturing will no longer let conventional sequential processors get faster year after year, as they have for so long (roughly doubling in speed every 18 months for many years). So all programs that need to run faster will have to become parallel programs. As multi-core processors and cluster systems have become ubiquitous, the demand for parallelization methods and technologies is also increasing. Parallel computer architecture is a field related to the development of these methods and computing technologies. Parallelism can be applied to different levels of a computer system and different challenges and solutions exist. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
[Corresponding Learning Outcomes] (A)Graduates are aware of their professional and ethical responsibilities as an engineer, and are able to analyze societal requirements, and set, solve, and evaluate technical problems using information science technologies in society. [Competency Codes] C-PD-001, C-PD-002, C-PD-003, C-PD-004, C-PD-005 The objective of this course is to understand the basic knowledge for designing and evaluating parallel computer architectures. The class will focus on understanding the elements that characterize parallel architectures, technical challenges, and possible solutions. Exercises in parallel programming will provide an understanding of parallel architectures through actual programming. |
| 授業スケジュール ／Class schedule |
1 Introduction to Parallel Computing 2 On Floating-point Arithmetic 3 Single Processor and Memory Hierarchy 4 Single Processor Performance Tuning(1) 5 Single Processor Performance Tuning(2) 6 Parallel and High Performance Computing 7 Shared Memory Parallel Computers 8 Distributed Memory Parallel Computers 9 Parallel Programming 10 Multi-core and Many-core Architectures(1) 11 Multi-core and Many-core Architectures(2) 12 Multi-core and Many-core Architectures(3) 13 Applications of Graphic Processing Units 14 AI and Super Computing Each class, a lecture (2 periods) fowllowd by an exersice class (1 period). Before the opening of the course : Review the classes "Computer Architecture" and "Operationg System" for roughly 20 - 30 hr. Pre-class Learning : Review the previous lecture for 1 - 2 hr. Post-class Learning : Continue to solve exercise problems and submit reports for 3 - 4 hr. |
| 教科書 ／Textbook(s) |
The lecture slides will be available in the LMS. |
| 成績評価の方法・基準 ／Grading method/criteria |
There is no final exam for this course. The grade will be based solely on the content of the report. |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
2.0 |
| 責任者 ／Coordinator |
KOHIRA Yukihide |
| 担当教員名 ／Instructor |
KOHIRA Yukihide |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
Courses preferred to be learned prior to this course (This course assumes understanding of entire or partial content of the following courses) LI13 CSE Exercise I (L05 CSE laboratories) NS04 Semiconductor Devices FU04 Logic Circuit Design (F04 Logic Circuit Design). |
| 更新日／Last updated on | 2026/02/04 |
|---|---|
| 授業の概要 ／Course outline |
Due to progress of LSI technology, developing electronics and advancing performance are achieved. Although the speed of a transistor is improved by the progress of process technology in LSI, it increases the routing delay. Since the routing delay is determined by layout process, it is important to understand the knowledge about layout design. In this class, students learn the knowledge of the LSI design. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
[Corresponding Learning Outcomes] (A)Graduates are aware of their professional and ethical responsibilities as an engineer, and are able to analyze societal requirements, and set, solve, and evaluate technical problems using information science technologies in society. [Competency Code] C-AR-007 1. Students will be able to understand the knowledge of the LSI design. 2. Students will be able to understand how to determine the LSI circuit performance and the power consumption. 3. Students will be able to understand how to design, evaluate, and verify LSI circuits by applying LSI design flow from logic synthesis to layout design in CAD tools. |
| 授業スケジュール ／Class schedule |
Each class will be conducted with the first two periods in a lecture format and the remaining two periods in an exercise format. (The course consists of a total of seven classes.) Lecture 1. Introduction 2. Review of semiconductor devices (CMOS Logic) 3. LSI design flow, memory 4. LSI layout design 5. Performance of CMOS circuits 6. Power consumption of CMOS circuits 7. Scaling Exercise 1-2. CMOS circuit design in transistor level 3-5. Layout design for CMOS circuits (Full custom design) 6-7. Layout design for CMOS circuits (Design automation) # The slots for lectures and exercises are changed in the progress of lectures. [Preparation and Review] Lecture and exercise materials will be made available before each class. Students are expected to review the lecture and exercise materials in advance of each class. The recommended amount of time for preparation for each class is approximately one hour. After each class, students should review the lecture materials (approximately two hours) and complete the exercise assignments (approximately six hours). |
| 教科書 ／Textbook(s) |
牧野 博之，益子 洋治，山本 秀和「半導体LSI技術」共立出版 |
| 成績評価の方法・基準 ／Grading method/criteria |
The plan of evaluation is as follows: Final examination: 60% Exercises: 40% Additionally, if a student is absent, the final score is reduced. |
| 履修上の留意点 ／Note for course registration |
Students are required to have the knowledge of the following courses: LI13 CSE Exercise I (L05 CSE laboratories), NS04 Semiconductor Devices and FU04 Logic Circuit Design (F04 Logic Circuit Design). |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Reference 國枝 博昭「集積回路設計入門」コロナ社 |
| Open Competency Codes Table Back |
| 開講学期 ／Semester |
2026年度／Academic Year 2学期 ／Second Quarter |
|---|---|
| 対象学年 ／Course for; |
3rd year |
| 単位数 ／Credits |
3.0 |
| 責任者 ／Coordinator |
SAITO Hiroshi |
| 担当教員名 ／Instructor |
SAITO Hiroshi, TOMIOKA Yoichi |
| 推奨トラック ／Recommended track |
－ |
| 先修科目 ／Essential courses |
Courses preferred to be learned prior to this course (This course assumes understanding of entire or partial content of the following courses) FU04 Logic Circuit Design |
| 更新日／Last updated on | 2026/01/28 |
|---|---|
| 授業の概要 ／Course outline |
In digital integrated circuits such as processors, the almost all design starts from modeling functional requirements using a hardware description language (HDL). A circuit is synthesized from the model by using electronic design automation (EDA) tools. Therefore, it is important to know how to model functional requirements using an HDL and how EDA tools synthesize digital integrated circuits. |
| 授業の目的と到達目標 ／Objectives and attainment goals |
[Corresponding Learning Outcomes] (A)Graduates are aware of their professional and ethical responsibilities as an engineer, and are able to analyze societal requirements, and set, solve, and evaluate technical problems using information science technologies in society. [Competency code] C-AR-009, C-AR-010 This course is an advanced course for logic circuit design. In lectures, students study a modeling method for digital integrated circuits using an HDL, the overview of logic synthesis tool, and a verification method for the designed circuits. In exercises, students model circuits using an HDL, synthesize logic circuits using an EDA tool. In addition, students implement the designed logic circuits on a field programmable gate array (FPGA). The performance of the implemented circuits is evaluated on an FPGA board. |
| 授業スケジュール ／Class schedule |
[Class format] Each class consists of 3 periods (50 minutes each), including 1 lecture period and 2 exercise periods. [Schedule] 1. Introduction 2. Review of logic circuit design 3. Verilog Hardware Description Language (Verilog HDL) 4. Modeling using Verilog HDL 5. Overview of logic synthesis 1 6. Overview of logic synthesis 2 7. Two-level logic minimization 8. Multi-level logic optimization 9. Technology mapping 10. Logic synthesis for FPGAs 11. Sequential circuit synthesis 12. Logic verification and static timing analysis 13. Summary 14. Others Exercises (100 min) 1. How to use Intel Quartus Prime? 2. How to use ModelSim? 3, 4. Modeling and synthesis of basic circuits using Verilog HDL 5, 6, 7, 8, 9. Modeling and synthesis of a counter and implementation on an FPGA board 10, 11, 12, 13, 14. Modeling and synthesis of a processor [Pre-Class learning] Read the lecture and exercise materials. If anything is unclear, research it online or with other resources. [Post-Class learning] Read the lecture materials to deepen your understanding. Complete any assigned tasks. If exercises were not finished during class, finish them and prepare for the report. |
| 教科書 ／Textbook(s) |
Not assigned |
| 成績評価の方法・基準 ／Grading method/criteria |
Reports (45%) and final examination (55%) 1. You can take the examinations if your absent is authorized absence 2. No re-examination for "D" evaluation 3. No credit is given if you do not take the final examination or submit any reports |
| 参考(授業ホームページ、図書など) ／Reference (course website, literature, etc.) |
Reference (in Japanese) Miyama, Kitagawa, Akita, and Suzuki, "VLSI Designs using HDL", Kyoritsu pub. |