1. Project Description

The shifts in hardware and software technologies force designers and users to look for microarchitectures that process instructions stream with high performance and low-power consumption. In order to achieve high performance, microarchitecture research has emphasized instruction-level parallelism processing, which has established in superscalar architecture without major changes to software. Since the program contains no explicit information about available ILP, it must be discovered by the hardware, which must construct a plan of actions for exploiting parallelism. In short, computers have thus far achieved this goal at the expense of tremendous hardware complexity – a complexity that has grown so large as to challenge the industry's ability to deliver ever-higher performance.

This project focuses on the research about a novel low power and high performance parallel processor processor based on Queue computation model, where Queue programs are generated by traversing a given data flow graph using level order traversal. The Queue processor uses a circular queue-register to manipulates operands and results, and exploits parallelism dynamically with "little efforts" when compared with conventional architectures. The nonexistence of false dependencies allows programs to expose maximum parallelism that the queue processor can execute without complex and power-hungry hardware such as register renaming and large instruction windows. Parallel processing allows queue processors to speed-up the execution of applications. We are researching and developing a complete tool-chain for this promising computing model consisting of: compiler, assembler, functional and cycle accurate simulator, and hardware design.

2. Members:

• Faculty: Prof. Ben Abdallah Abderazek
• Former members: Hiroki Hoshino, M.S. (2010); Shunichi Kato, B.S.(2010); Yuuki Omoto, B.S.(2009), Others.

2. Publications

• Hiroki Hoshino, A. Ben Abdallah, Development of Parallel Queue Processor Architecture and its Integrated Development Environment, Master's Thesis, The University of Aizu, Feb. 2011. 

• Masashi Masuda, A. Ben Abdallah, Produced Order Queue Compiler Design, Mater's Thesis, The University of Aizu, Feb. 2011.
  

• A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda,Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture, The Journal of supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.

• A. Canedo, A. Ben　Abdallah, and M. Sowa, ''Efficient Compilation for Queue Size Constrained Queue Processors, The Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.

• A. Canedo, A. Ben　Abdallah, and M. Sowa, "Compiler Support for Code Size Reduction using a Queue-based Processor", Transactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009.

• A. Ben Abdallah, A. Canedo, T. Yoshinga, and M. Sowa, The QC-2 Parallel Queue Processor Architecture, Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.

• A. Canedo, A. Ben　Abdallah, and M. Sowa, "A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model", Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007.

• A. Ben　Abdallah, Sotaro Kawata, and M. Sowa, "Design and Architecture for an Embedded 32-bit QueueCore", Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.

• A. Ben　Abdallah, T. Yoshinaga, and M. Sowa, "High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core", Journal of supercomputing, Vol. 38, Number 1, pp. 3-15, 2006

• M. Masuda, A. Ben Abdallah, A. Canedo, “Software and Hardware Design Issues for Low Complexity High-Performance Processor Architecture”, The 38th International Conference on Parallel Processing Workshops, pp. 558-565, 2009

• M. Masuda, A. Canedo, A. Ben Abdallah, "Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture," The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009.(Best Presentation Award).

• H. Hoshino, A. Ben　Abdallah, and K. Kuroda, "Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model", IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.

• A. Canedo, A. Ben　Abdallah, and M. Sowa, "Quantitative Evaluation of Common Subexpression Elimination on Queue Machines", Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.

• A. Canedo, A. Ben　Abdallah, and M. Sowa, "Queue Register File Optimization Algorithm for QueueCore Processor", Proc. IEEE 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.

• A. Canedo,A. Ben　Abdallah, and M. Sowa, "An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model", Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007

• A. Canedo, A. Ben Abdallah, and M. Sowa, "Compiler Framework for an Embedded 32-bit Queue Processor" , Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.

• A. Ben　Abdallah, T. Yoshinaga, and M. Sowa, "High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core", Journal of supercomputing, Vol. 38, Number 1, pp. 3-15, 2006.

• A. Ben　Abdallah, Sotaro Kawata, and M. Sowa, "Design and Architecture for an Embedded 32-bit QueueCore", Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.

• M. Sowa, A. Ben　Abdallah, and T. Yoshinaga, ''Processor Architecture Based on Produced Order Computation Model'', '''Journal of Supercomputing, Vol. 32,No. 3, pp. 217-229, June 2005.
• A. Ben　Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, "Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005.

• A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, "PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL", Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.

• A. Ben　Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Architectural Issues in the Design of a High Performance Parallel Queue Processor", Proc. of 4th Tunisia-Japan Symposium on Science and Technology (TJASSST2003), April 2003.

• A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)", Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.

• A. Ben　Abdallah, K. Nikolova, and M. Sowa, "FARM-Queue Mode: On a Practical Queue Execution Model", Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, pp.939-944, July 2001.

• A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, "FARM QUEUE MODE: On a Practical Queue Execution Model (QEM)", TIWSS’01, October 2001.

• A. Ben Abdallah, K. Nikolova, and M. Sowa, "FARM-Queue Execution Model: Towards an Alternative Computing Paradigm", Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000.

• A. Ben Abdallah, M. Sarem., and M. Sowa, "Acyclic DFG on a Queue Machine", Proc. of JSPP, Tokyo, pp.119-120, 2000.

• A. Ben　Abdallah, and M. Sowa, "DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor", Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT'99), pp.131-136, Oct.1999.

• Hiroki Hoshino, Abderazek Ben Abdallah and Kenichi Kuroda. Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.16-22, Dec. 2008.

• A. Ben Abdallah, et. all "Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005

• A. Ben Abdallah, et. all,"Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme", IEEE computer Society, Proc. of the The 7th High Perfomance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.

Others

• QSoC - Queue System on Chip on FPGA, Technical Report, ASL, UoA, Jan. 2010.
• Qasm - User Friendly Assembler for Queue Computers, Technical Report, ASL,UoA, 2010.
• QC-3 Data Path, Technical Report, ASL, UoA, Oct. 2009
• QueueCore - The Strong Wave!, Technical report, IS, UEC, May 2007
• QueueCore Instruction Set Architecture,Technical Report, IS, UEC, Jan. 2003.
• QC-1 Processing Stages Algorithms, Technical Report, IS, UEC, Oct. 2003.

The complete developed tool-chain is made of compiler (QCom), assembler(Qasm), functional and cycle accurate simulator (QSim), and soft-core hardware processor (QueueCore (QC-1, QC-2, and QC-3)). If you are interested in this project, please contact Prof. Ben Abdallah for further details.

Note: Your use of any information or materials on this website is entirely at your own risk, for which we shall not be liable.

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(c) Ben Abdallah Abderazek, 2000-2009.