// Verilog stimulus file.
// Please do not create a module in this file.

// Default verilog stimulus. 

initial
begin 

`define R_TYPE 6'b000000
`define ADDI 6'b001000
`define ANDI 6'b001100
`define ORI 6'b001101
`define LW 6'b100011
`define SW 6'b101011
`define BEQ 6'b000100
`define SLTI 6'b001010
`define J 6'b000010
`define ADD_FUNCT 6'b100000
`define SUB_FUNCT 6'b100010
`define AND_FUNCT 6'b100100
`define OR_FUNCT 6'b100101
`define SLT_FUNCT 6'b101010



// instruction codes labels instructions 

IMem.cell['h0] ={`LW, 5'd0, 5'd1, 16'h1000}; //lw $1, 'h1000($0) ;
IMem.cell['h4] ={`LW, 5'd0, 5'd2, 16'h1004}; //lw $2, 'h1004($0) ;
IMem.cell['h8] ={`LW, 5'd0, 5'd3, 16'h1008}; //lw $3, 'h1008($0) ;
IMem.cell['hc] ={`SW, 5'd3, 5'd1, 16'h1000}; //sw $1, 'h1000($3) ; 

IMem.cell['h10]={`R_TYPE, 5'd1, 5'd2, 5'd4, 5'd0, `ADD_FUNCT}; //add $4, $1, $2 ; 
IMem.cell['h14]={`SW, 5'd0, 5'd4, 16'h1010}; //sw $4, 'h1010($0) ; 
IMem.cell['h18]={`R_TYPE, 5'd1, 5'd2, 5'd5, 5'd0, `SUB_FUNCT}; //sub $5, $1, $2 ; 
IMem.cell['h1c]={`SW, 5'd0, 5'd5, 16'h1014}; //sw $5, 'h1014($0) ; 

IMem.cell['h20]={`ADDI, 5'd1, 5'd6, 16'h0100}; //addi $6, $1, 'h100 ; 
IMem.cell['h24]={`SW, 5'd0, 5'd6, 16'h1018}; //sw $6, 'h1018($0) ; 
IMem.cell['h28]={`R_TYPE, 5'd1, 5'd2, 5'd7, 5'd0, `AND_FUNCT}; //and $7, $1, $2 ; 
IMem.cell['h2c]={`SW, 5'd0, 5'd7, 16'h101c}; //sw $7, 'h101c($0) ; 

IMem.cell['h30]={`R_TYPE, 5'd1, 5'd2, 5'd8, 5'd0, `OR_FUNCT}; //or $8, $1, $2 ; 
IMem.cell['h34]={`SW, 5'd0, 5'd8, 16'h1020}; //sw $8, 'h120($0) ; 
IMem.cell['h38]={`ANDI, 5'd1, 5'd9, 16'h0100}; //andi $9, $1, 'h100 ; 
IMem.cell['h3c]={`SW, 5'd0, 5'd9, 16'h1024}; //sw $9, 'h1024($0) ; 

IMem.cell['h40]={`ORI, 5'd1, 5'd10, 16'h0100}; //ori $10, $1, 'h10 ; 
IMem.cell['h44]={`SW, 5'd0, 5'd10, 16'h1028}; //sw $10, 'h1028($0); 
IMem.cell['h48]={`ADDI, 5'd0, 5'd11, 16'h0002}; //addi $11, $0, 2 ;
IMem.cell['h4c]={`ADDI, 5'd0, 5'd12, 16'h0004}; //addi $12, $0, 4 ; 

IMem.cell['h50]={`ADDI, 5'd11, 5'd11, 16'h0002}; //addi $11, $11,2 ; 
IMem.cell['h54]={`BEQ, 5'd11, 5'd12, 16'hfffe}; //beq $11, $12, -8 ; 
IMem.cell['h58]={`SW, 5'd0, 5'd11, 16'h102c}; //sw $11, 'h102c($0); 
IMem.cell['h5c]={`R_TYPE, 5'd1, 5'd2, 5'd13, 5'd0, `SLT_FUNCT}; //slt $13, $1,$2 ; 

IMem.cell['h60]={`SW, 5'd0, 5'd13, 16'h1030}; //sw $13, 'h1030($0); 
IMem.cell['h64]={`R_TYPE, 5'd2, 5'd1, 5'd14, 5'd0, `SLT_FUNCT}; //slt $14, $2,$1 ; 
IMem.cell['h68]={`SW, 5'd0, 5'd14, 16'h1034}; //sw $14, 'h1034($0); 
IMem.cell['h6c]={`SLTI, 5'd1, 5'd15, 16'h1000}; //slti $15, $1,'h1000 ; 

IMem.cell['h70]={`SW, 5'd0, 5'd15, 16'h1038}; //sw $15, 'h1038($0); 
IMem.cell['h74]={`SLTI, 5'd1, 5'd16, 16'h5000}; //slti $16, $1,'h5000 ; 
IMem.cell['h78]={`SW, 5'd0, 5'd16, 16'h103c}; //sw $16, 'h103c($0); 
IMem.cell['h7c]={`BEQ, 5'd0, 5'd0, 16'hffff}; //beq $0, $0, -4 ; 


Mem.cell['h1000]='h335e;
Mem.cell['h1004]='h0d21;
Mem.cell['h1008]='hc;
Mem.cell['h100c]='h0;
Mem.cell['h1010]='h0;
Mem.cell['h1014]='h0;
Mem.cell['h1018]='h0;
Mem.cell['h101c]='h0;
Mem.cell['h1020]='h0;
Mem.cell['h1024]='h0;
Mem.cell['h1028]='h0;
Mem.cell['h102c]='h0;
Mem.cell['h1030]='h0;
Mem.cell['h1034]='h0;
Mem.cell['h1038]='h0;

CK = 1'b1;
CLR = 1'b1;
#110
CLR = 1'b0;
#17000
$display("RESULT:");
$display("sw: 335e: %x",Mem.cell['h100c]);
$display("add: 407f: %x",Mem.cell['h1010]);
$display("sub: 263d: %x",Mem.cell['h1014]);
$display("addi: 345e: %x",Mem.cell['h1018]);
$display("and: 100: %x",Mem.cell['h101c]);
$display("or: 3f7f: %x",Mem.cell['h1020]);
$display("andi: 100: %x",Mem.cell['h1024]);
$display("ori: 335e: %x",Mem.cell['h1028]);
$display("beq: 6: %x",Mem.cell['h102c]);
$display("slt: 0: %x",Mem.cell['h1030]);
$display("slt: 1: %x",Mem.cell['h1034]);
$display("slti: 0: %x",Mem.cell['h1038]);
$display("slti: 1: %x",Mem.cell['h103c]);
$finish;
end

always #250 CK=~CK;