// Verilog stimulus file.
// Please do not create a module in this file.

// Default verilog stimulus. 

initial
begin 

`define R_TYPE     6'b000000
`define ADDI       6'b001000
`define ANDI       6'b001100
`define ORI        6'b001101
`define LW         6'b100011
`define SW         6'b101011
`define BEQ        6'b000100
`define SLTI       6'b001010
`define J          6'b000010
`define ADD_FUNCT  6'b100000
`define SUB_FUNCT  6'b100010
`define AND_FUNCT  6'b100100
`define OR_FUNCT   6'b100101
`define SLT_FUNCT  6'b101010



//                      instruction codes                       labels  instructions    ; 

IMem.cell['h0] ={`LW,     5'd0,  5'd2,  16'h1000};                  //lw   $2, 'h1000($0) ;
IMem.cell['h4] ={`LW,     5'd0,  5'd3,  16'h1004};                  //lw   $3, 'h1004($0) ;
IMem.cell['h8] ={`LW,     5'd0,  5'd4,  16'h1008};                  //lw   $4, 'h1008($0) ;
IMem.cell['hc] ={`LW,     5'd0,  5'd5,  16'h100c};                  //lw   $5, 'h100c($0) ;

IMem.cell['h10] ={`LW,     5'd0,  5'd6,  16'h1010};                  //lw  $6, 'h1010($0) ;
IMem.cell['h14] ={`LW,     5'd0,  5'd7,  16'h1014};                  //lw  $7, 'h1014($0) ;
IMem.cell['h18] ={`LW,     5'd0,  5'd8,  16'h1018};                  //lw  $8, 'h1018($0) ;
IMem.cell['h1c] ={`LW,     5'd0,  5'd9,  16'h101c};                  //lw  $9, 'h101c($0) ;

IMem.cell['h20]={`R_TYPE, 5'd2,  5'd3,  5'd11, 5'd0, `SUB_FUNCT};    //sub $11, $2, $3    ;
IMem.cell['h24]={`R_TYPE, 5'd4,  5'd5,  5'd12, 5'd0, `AND_FUNCT};    //and $12, $4, $5    ;
IMem.cell['h28]={`R_TYPE, 5'd6,  5'd7,  5'd13, 5'd0, `OR_FUNCT};     //or  $13, $6, $7    ;
IMem.cell['h2c]={`R_TYPE, 5'd8,  5'd9,  5'd14, 5'd0, `ADD_FUNCT};    //add $14, $8, $9    ;

IMem.cell['h30]={`SW,     5'd0,  5'd11,  16'h1020};                  //sw  $11, 'h1020($0);
IMem.cell['h34]={`SW,     5'd0,  5'd12,  16'h1024};                  //sw  $12, 'h1024($0);
IMem.cell['h38]={`SW,     5'd0,  5'd13,  16'h1028};                  //sw  $13, 'h1028($0);
IMem.cell['h3c]={`SW,     5'd0,  5'd14,  16'h102c};                  //sw  $14, 'h102c($0);

IMem.cell['h40]={`BEQ,    5'd0,  5'd0,   16'hffff};                  //beq  $0, $0, -4    ;

Mem.cell['h1000]='hd8a3b8d4;
Mem.cell['h1004]='h63b9d6f2;
Mem.cell['h1008]='hd8a3b8d4;
Mem.cell['h100c]='h63b9d6f2;
Mem.cell['h1010]='hd8a3b8d4;
Mem.cell['h1014]='h63b9d6f2;
Mem.cell['h1018]='hd8a3b8d4;
Mem.cell['h101c]='h63b9d6f2;
Mem.cell['h1020]='h0;
Mem.cell['h1024]='h0;
Mem.cell['h1028]='h0;
Mem.cell['h102c]='h0;
Mem.cell['h1030]='h0;
Mem.cell['h1034]='h0;
Mem.cell['h1038]='h0;

   CK = 1'b1;
   CLR = 1'b1;
   #110
   CLR = 1'b0;
   #3000
   $display("RESULT:");
   $display("sub:   74e9e1e2: %x",Mem.cell['h1020]);
   $display("and:   40a190d0: %x",Mem.cell['h1024]);
   $display("or:    fbbbfef6: %x",Mem.cell['h1028]);
   $display("add:   3c5d8fc6: %x",Mem.cell['h102c]);
   $finish;
end

always #50 CK=~CK;