Exercise 1 Verilog Design of a 32-bit ALU

32-bit ALU

ALUOp	Function	Result
000	and	A and B
001	or	A or B
010	add	A + B
110	subtract	A - B
111	set on less than	A<B?1:0

Working steps for Verilog Design of a 32-bit ALU

Create library
- Start Cadence design entry: icds&. It will display CIW(Command Interpreter Window).
- Select File -> New -> Library in CIW window.
  It will display the following window.
  - Input library name(archi).
  - Select Don't need a techfile.
  - Click OK.
You can store all of your designs in this library later.
Create module for 32-bit ALU
- Select File -> New -> Cellview in CIW window.
  It will display the following window.
- Select Library Name(archi).
- Input Cell Name(alu32).
- Input View Name(behavioral).
- Select Tool(Verilog-Editor).
- Click OK.
- Text edit(nemacs) will be started.
- Input the following verilog file. // Verilog HDL for "archi", "alu32" "behavioral" `define ALULEN 31 module alu32(Result,ALUOp,A,B,Zero); output [`ALULEN:0] Result; reg [`ALULEN:0] Result1; output Zero; reg Zero; input [2:0] ALUOp; input [`ALULEN:0] A,B; always @(A or B or ALUOp) begin case (ALUOp) 3'b000: Result1 = A & B ; // AND 3'b001: Result1 = A | B ; // OR // add your code here for addition, subtraction and set on less than endcase // add your code here for Zero detect end assign Result=Result1; endmodule
- After you save the file and quit the editor the system will check errors automatically. You need to update your file until there is no error reported.
- Click OK on the following window. The symbol of alu32 will be created.

Simulation

Select File -> Open in CIW window.
It will display the following window.
Select Library Name(archi).
Input Cell Name(alu32).
Select View Name(behavioral).
Select Mode(read).
Click OK.
It will display the following window.
Select Tools -> Verilog-XL Click OK, Verilog-XL will be started.
Select Stimulus -> Verilog.... Click Yes, It will display the following window.
Select testfixture.verilog, click Apply.
Click Copy, it will display the following window.
Click button of Make Current Test Fixture and Check verilog Syntax, click Apply.
Select testfixture.new, click Edit, click OK.

Input the simulation file(testfixture.new). //

// Verilog stimulus file.
// Please do not create a module in this file.
 
  
// Default verilog stimulus. 

initial
begin 
//and     
$display("AND: ALU control input: 000");
$display("    A        B    Zero   Result");
   ALUOp[2:0] = 3'b000;
   A[31:0] = 32'h00000000;
   B[31:0] = 32'h00000000;
   #500
   $display("%x %x   %x  %x",A,B,Zero,Result); 
   A[31:0] = 32'h0f0f0f0f;
   B[31:0] = 32'hf0f0f0f0;
   #500
   $display("%x %x   %x  %x",A,B,Zero,Result); 
   A[31:0] = 32'hf0f0f0f0;
   B[31:0] = 32'h0f0f0f0f;
   #500
   $display("%x %x   %x  %x",A,B,Zero,Result); 
   A[31:0] = 32'hffffffff;
   B[31:0] = 32'hffffffff;
   #500
   $display("%x %x   %x  %x",A,B,Zero,Result); 
   A[31:0] = 32'hd8a3b8d4;
   B[31:0] = 32'h63b9d6f2;
   #500
   $display("%x %x   %x 40a190d0 %x",A,B,Zero,Result); 

//add your code here for or option refer to input data in Simulation table.

//add your code here for addition refer to input data in Simulation table.

//add your code here for subtraction refer to input data in Simulation table.

//add your code here for set on less refer to input data in Simulation table. 

   $finish;
end

Click Start Interactive button in Verilog-XL window.
Click Continue button in Verilog-XL window.
Click View Waveforms button in Verilog-XL window.
You will see the result in Verilog-XL window directly. Also you can open the cwave window to see the simulation result using waveform. You can compare A, B, Zero and Result with the simulation table. If they are not same you will need to check the verilog file of alu32 and the simulation file(testfixture.new).
How to display signals in the waveform window

The simulation table.
An example of the simulation result of ALU.