Lecture   Data Hazards and Forwarding

Reading materials of this Lecture:

  1. Chapter 6.4 Data Hazards and Forwarding in the text book.

Section 1 Examples of Data Hazards


Example 1 :
       add     $s0,    $t0,    $t1
       sub      $t2,    $s0,    $t3

In the example, the second instruction is dependent on the result
in $s0 of the first instruction:
     if $s0 = -5 before add
         $s0 =  8   after add
     then the value 8 should be used in the second instruction sub.
 

Draw the multiple clock cycle pipeline diagram for the execution:

                           Time
 Execution           Time       CC1     CC2      CC3       CC4          CC5        CC6
 order
add $s0, $t0, $t1                    IF ---ID---EX---MEM--WB

value in $s0                             -5        -5        -5          -5          -5/8         8

sub  $t2, $s0, $t3                                 IF ---ID---EX---MEM---WB
 

    In which clock cycle add writes to $s0?     Clock 5
    In which clock cycle sub reads $s0?            Clock 3

For sub instruction, the value in $s0 has to be read in its ID stage (CC3).
However, the value in $s0 in CC3 is still -5 and not the correct value
8. We can only have the correct value in $s0 at the end of clock 5 (CC5).

The dependency goes from CC5 ---> CC3 (backward)

Data hazards: an instruction depends on the results of a previous instruction
                           that is still in the pipeline

Another definition of data hazards:
    dependencies that go backward in time are data hazards

Software solution:
    Compiler can insert two independent instructions or two "nop" instruction
    between add and sub to make hazard  disappear.
 

       add     $s0,    $t0,    $t1
       nop
       nop
       sub      $t2,    $s0,    $t3

nop: no operation. In MIPS, "nop" represents sll $0, $0, 0, which shifts register 0
         left 0 bits.
 

Example 3: A sequence with many dependencies

      sub    $2,      $1,   $3                      #  register $2 is written by sub
      and   $12,    $2,   $5                      #  the first operand ($2) depend on sub
      or      $13,    $6,   $2                      #  the second operand ($2) depend on sub
      add   $14,    $2,   $2                      #  the first operand and the second ($2) depend on sub
      sw     $15,    1000($2)                  #  base ($2) depend on sub

Draw the multiple clock cycle pipeline diagram for the execution:

Four dependency lines:
                                                          data hazard
a. sub-and: from CC5 to CC3,        Yes
b. sub-or   : from CC5 to CC4,        Yes
c. sub-add: from CC5 to CC5,        Not
d. sub-sw  : from CC5 to CC6,        Not

Section 2 Forwarding


Forwarding: get the missing item early from the internal resources.

Two steps to forward:
    (1) how to detect data hazards
    (2) how to forward the data

How to detect data hazards:

                                  read                                  write
    an instruction  ----> Register File  <---- earlier instructions
           in EX                                                                     in MEM or WB
                                              the same register
 
    1. EX hazards

                                             read                                  write
     an instruction in EX ----> Register File  <----  instruction in MEM
 
    1a. EX/MEM.RegisterRd = ID/EX.RegisterRs
    1b. EX/MEM.RegisterRd = ID/EX.RegisterRt

    EX/MEM.RegisterRd : the write register whose value in EX/MEM register

    ID/EX.RegisterRs: the first register whose value in ID/EX register

    ID/EX.RegisterRt: the second register whose value in ID/EX register

   2. MEM hazards

                                           read                                   write
   an instruction  in EX----> Register File  <---- earlier instruction in WB
 
   2a. MEM/WB.RegisterRd = ID/EX.RegisterRs
   2b. MEM/WB.RegisterRd = ID/EX.RegisterRt

MEM/WB.RegisterRd : the write register whose value in MEM/WB register

In Example 3:
(1) sub-and is EX hazard
       EX/MEM.RegisterRd = ID/EX.RegisterRs = 2

(2) sub-or  is MEM hazard
       MEM/WB.RegisterRd = ID/EX.RegisterRs = 2

(3) Two dependencies between sub-add are not hazards because the
        Register File supplies the proper data during the ID stage of of add.

       Register File Forwarding:
          What will be done when a register is read and written in the same
          clock cycle?
          Assume that write happens in the first half of the clock cycle and
           read takes place in the second half of the clock cycle so that read
           outputs what is written in the same clock cycle.
(4) No data hazard between sub and sw because sw read $2 in the clock
       cycle after sub writes $2

Section 3 How to Forward Data

Control values for the forwarding multiplexors:
 
 Mux control          Source               Explanation

ForwardA =  00     ID/EX               The first ALU input from REgister File
ForwardA = 10      EX/MEM         The first ALU input is forwarded from the prior ALU result
ForwardA =  01     MEM/WB       The first ALU input is forwarded from Data Memory
                                                              or an earlier ALU result.

ForwardB =  00     ID/EX               The second ALU input from REgister File
ForwardB = 10      EX/MEM         The second ALU input is forwarded from the prior ALU result
ForwardB =  01     MEM/WB       The second ALU input is forwarded from Data Memory
                                                              or an earlier ALU result.
 
 
 

1. EX hazards

if (EX/MEM.RegWrite == 1
      and EX/MEM.RegisterRd != 0
      and EX/MEM.RegisterRd = ID/EX.RegisterRs) ForwardA = 10

if (EX/MEM.RegWrite == 1
      and EX/MEM.RegisterRd != 0
      and EX/MEM.RegisterRd = ID/EX.RegisterRt) ForwardB = 10

2. MEM hazards

if (MEM/WB.RegWrite == 1
      and MEM/WB.RegisterRd != 0
      and MEM/WB.RegisterRd = ID/EX.RegisterRs) ForwardA = 01

if (MEM/WB.RegWrite == 1
      and MEM/WB.RegisterRd != 0
      and MEM/WB.RegisterRd = ID/EX.RegisterRt) ForwardB = 01

What if on data hazard matches both conditions in EX hazard
and MEM hazard? The data hazard should be treated as EX hazard
rather than MEM hazard.

if (MEM/WB.RegWrite == 1
      and MEM/WB.RegisterRd != 0
      and EX/MEM.RegisterRd != ID/EX.RegisterRs
      and MEM/WB.RegisterRd = ID/EX.RegisterRs) ForwardA = 01

if (MEM/WB.RegWrite == 1
      and MEM/WB.RegisterRd != 0
      and EX/MEM.RegisterRd != ID/EX.RegisterRt
      and MEM/WB.RegisterRd = ID/EX.RegisterRt) ForwardB = 01