Reading materials of Lecture 2:
1. Chapter 4.1 Introduction
in the text book.
2. Chapter 4.2 Signed and Unsigned
Numbers in the text book.
3. Chapter 4.3 Addition and Subtractions
in the text book.
4. Chapter 4.4 logical Operation
in the text book.
5. Chapter 4.5 Constructing an Arithmetic
Logic Unit in the text book.
Design 1 1-bit logical unit for AND and OR
See Figure 4.9
Design 2 1-bit Adder
See Figures 4.10, 4.11, 4.12, and 4.13.
Design 3 1-bit ALU that performs AND, OR, and addition
See Figure 4.14.
Design 4 Verilog Design of 1-bit ALU
module ALU_1_bit(a, b, operation, Result);
input a, b;
input [1:0] operation;
output Result;
reg Result;
always@(a or b or operation)
begin
case (operation)
2'b00: Result = a & b; // AND
2'b01: Result = a | b; // OR
2'b10: Result = a + b; // addition
2'b11: Result = a - b; // subtraction
endcase
end
endmodule
Design 5 Schematic design of 32-bit ALU
See Figure 4.15.
Design 6 Verilog Design of 32-bit ALU
module ALU_32_bit(a, b, operation, Result);
input [31:0] a;
input [31:0] b;
input [1:0] operation;
output [31:0]Result;
reg [31:0] Result;
always@(a or b or operation)
begin
case (operation)
2'b00: Result = a & b; // AND
2'b01: Result = a | b; // OR
2'b10: Result = a + b; // addition
2'b11: Result = a - b; // subtraction
endcase
end
endmodule
Three other operations:
(1) how to perform subtraction;
(2) how to perform comparison;
(3) how to test the result is Zero or not.
By two's complement, negating a two's complement number is to
invert each bit and then add 1:
a - b = a + (-b) = a + (not b) + 1
For comparing rs with rt,
rs < rt <==> rs - rt < 0
only the sign bit of result of (rs - rt) is needed. In two's complement,
sign bit 1 means negative and 0 means positive.
For testing the Zero signal,
if Result == 0,
Zero = 1
else
Zero = 0