Computer Education Laboratory

Kenichi Kuroda Professor	Junji Kitamichi Associate Professor

The academic area of the laboratory mainly covers computer design methodology. Educational course design for VLSI design, formal verification and reconfigurable computing are the major themes of this lab. Education: We have been developing an education program of VLSI design based on VDEC (VLSI Design and Education Center) support. VDEC offers various kindsof design tools without license cost and accepts chip fabrication orders in low price. This program was started as an joint research with Prof. Shima, who left from this university in 2004, in Computer Architecture Laboratory in 2001. Web-based manuals for HDL design, verification, and layout tools have been developed and are being updated depending onVDEC support toos every year. Research: Various kinds of circuits based on PCA (one of dynamically reconfigurable devices) have been designed and implemented. For high productivity, library modules, similar to the standard cell libraries in the conventional VLSI design technology, have been developed and applied to applications for parallel processors, neural networks, and image compression. The Joint research with NTT has been carried out. Some of the results were publishedand presented at conferences. As to the traditional synchronous circuit technology, various applications such as bio-informatics and network security have been surveyed based on VDEC technology environment. Members of the Computer Education Laboratory Prof. Kenichi Kuroda: Before his coming to this university, he belonged to the NTT laboratories and he was engaged with the research on superconductor devices, SAW devices, and X-ray optics. He joined this university mid 1995. He received his Dr. Eng. from Tokyo University in 1991. He had been amember of the Computer Device Lab for 5 years and moved to this lab in summer 2000. After coming to this university, he was interested in VLSI design technology. Especially, dynamically reconfigurable devices such as PCA (Plastic Cell Architecture) are the current major research direction. Prof. Junji Kitamichi: He received the B.S. and Ph.D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Centor at Osaka University, where he was assistant Professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. His research interests include formal methods for VLSI design, design verification, hardware description language, dynamical reconfigurable architechtures, and real-time systems. Students : Research Topics Doctor Program Toshiyuki Ito : Processors on dynamically reconfigurable device PCA. Keigo Kurata : Artificial neural networks on PCA. Master Program : PCA related topics Atsushi Suzuki, Kae Suzuki, Ikko Tanaka, Hiroyuki Morita, Susumu Moro. Yoshuke Ikehata, Hironori Endo, Tomoki Kamiyama. Master Program : Application circuits and tool development Kenji Asano, Sou Inoue, Junichi Nakajima, Chizuru Saito, Hiroaki Tanba. Graduation Thesis Students : PCA related topics Tomoyuki Inoue, Tomoko Otsuka, Tomoyoshi Kanno, Yasuhiro Sugita. Graduation Thesis Students : Application circuits and tool development Norisato Ikeda, Yoshiharu Fujitsu, Mitsuhiro Honda, Koji Ueda, Shuichi Watanabe, Yutaka Watanabe.

Referred Proceeding Papers

[kitamiti-01:2004]	Junji Kitamichi, Junichi Nakajima, and Kenichi Kuroda. Proposal of Data Structure and Algorithms based on BDDs(Binary Decision Diagrams. InDA Synposium 2004, pages 235-240. DA Synposium, July 2004.
	We propose new data structure and algorithms for a restricted arithmetic with real number variables andoperations. In this restricted arithmetic, which consists of logical and real number variables and operators, we can describe specifications of real time systems and so forth.Proposed data structure is an extended BDD(Binary Decision Diagram), which is one of methods expressing Boolean functions. We also describe some algorithms forproposed data structure.
[kuroken-01:2004]	J. Kitamichi, J. Nakajima, and K. Kuroda. Proposal of Data Structure and Algorithms based on BDDs(Binary Decision Diagrams) for a Real Number Restricted Arithmetic. In Proc. of Design Automation Symposium 2004 (IPSJ Symp. Series 2004-11), pages 235-240. IPSJ, July 2004.
	We proposed new data structure and algorithms for a restrcted arithmetic with real number variables and operations. In this restricted arithmetic, which consists of logical and real number variables and operations, we can describe specifications of real time systems and so forth. Proposed data structure is an extended BDD(Binary Decision Diagram), which is one of methods expressing Boolean functions. We also describe some algorithms for proposed data structre.

Unreferred Papers

[kitamiti-02:2004]	Junji Kitamichi. Proposal of Data Structure based on BDDs(Binary Decision Diagrams) and Algorithms for an Integer Restricted Arithmetic. In IEICE Technical Report, SS2005-5, pages 25-30, 2004.
[kitamiti-03:2004]	Kenji Asano, Junji Kitamichi, and Kenichi Kuroda. Proposal of a Simulation Method for Dynamical Reconfigurable Architecture PCA using SystemC. InIPSG SIG Technical Reports 2004-SLDM-115, pages 53-58, 2004.
[kitamiti-04:2004]	Chizuru Saitou, Junji Kitamichi, and Kenichi Kuroda. Second SECONDS: Another SFL Design Environment - sflpar + SystemC. In 24-th PARTHENON Workshop, pages 31-40, 2004.
[kitamiti-05:2004]	Sou Inoue and Junji Kitamichi. Hardware Implementation of Dynamic-Programming Algorithm for Genome Homology Analaysis. In Proceedings of the 2004 IEICE Society Conference, AS-3-4, page 27, 2004.
[kitamiti-06:2004]	Susumu Moro, Junji Kitamichi, and Kenichi Kuroda. Description Language and Partitioning in Circuit Modeling for Fine Grain Dynamically Reconfigurable Logic Devices. In IPSG SIG Technical Reports, 4-th Reconfigurable System, pages 95-102, 2004.
[kitamiti-07:2004]	Kae Suzuki, Toshiyuki Ito, Junji Kitamichi, and Kenichi Kuroda. Design of Fast Wavelet Transform Circuits using Partial Hardware Reconfiguration on PCA. In IEICE Technical Report, CPSY2004-36, 2004.
[kitamiti-08:2004]	Tomoki Kamiyama, Ikko Tanaka, Susumu Moro, Junji Kitamichi, and Kenichi Kuroda. Proposal and Implementation of Framework for Self-Reproductive Application on PCA. In 25-th PARTHENON Workshop, pages 29-35, 2004.
[kitamiti-09:2004]	Junji Kitamichi, Chizuru Saitou, and Kenichi Kuroda. SFL for Asynchronus System and Consideration on some Themes about it. In 25 -th PARTHENON Workshop, pages 37-42, 2004.
[kitamiti-10:2004]	Tomoki Kamiyama, Keigo Kurata, Yousuke Ikehata, Junji Kitamichi, and Kenichi Kuroda. Proposal and Implementation of Framework for Self-Reproductive Applications on Dynamically Reconfigurable Device PCA. In IPSG SIG Technical Reports 2005-SLDM-118, pages 141-146, 2004.
[kitamiti-11:2004]	Sou Inoue, Junji Kitamichi, and Kenichi Kuroda. FPGA Implementation of Dynamic-Programming Algorithm for Genome Homoly Analaysis. In 2005 FPGA/PLD Conference, User Presentation, pages 7-12, 2005.
[kuroken-02:2004]	K. Asano, J. Kitamichi, and K. Kuroda. Proposal of a Simulation Method for Dynamical Reconfigurable Architecture PCA using System C. In Technical Report of IEICE, volume 2004-SLDM, pages 53-58, 2004.
	In this paper, we propose a simulation method for dynamical reconfigurable architecture PCA using SystemC. Using proposed method, we are able to verify the specifications from the level of system requirement to the concrete level at which the system performs on the FPGA devices. In this paper, we design Hamadard transform circuit, one of orthogonal transform, with step-wise refinement from system requirement level to concrete level at which the system runs on PCA, simulate each specification in SystemC and evaluate proposed method.
[kuroken-03:2004]	C. Saito, J. Kitamichi, and K. Kuroda. Second SECONDS: Another SFL Design Environment -sflpar + SystemC-. In Proc. of 24th PARTHENON Workshop, volume 2004, pages 31-40, 2004.
	Because SFL designed for synchronous circuits with a single global clock has simple language specifications, it is easy to design circuits with SFL; therefore, it is sufficiently attractive language for the design of recent large scale circuits. However, there are not suAEcient supporting software/hardware co-design environments and physical libraries for ASIC design using SFL. In this paper, we propose a new simulation environment for SFL using SystemC, one of the system description languages. Based on the proposed method, SFL description is equivalently converted to SystemC description, and the new simulation environment simulates converted SystemC description easily. The proposed system consists of a SFL-SystemC conversion part and a simulator part. We use a part of existing SFL parser for the conversion part. We confirm speedups in this simulation for a combinational circuit ad a sequential circuit described in SFL under the proposed environment. Moreover, we can use existing supporting tools for SystemC such as waveform editor or logic synthesizer by using this system. As a result we can co-simulate circuits with a lighter workload than the existing environment provides.
[kuroken-04:2004]	S. Inoue, J. Kitamichi, and K. Kuroda. Hardware Implementation of Dymamic-Programming Algorithm for Genome Homology Analysis. In IEICE Annual Conference of Basic and Boundary Fields Society, volume AS-3-4, pages S-27, 2004.
[kuroken-05:2004]	S. Moro, J. Kitamichi, and K. Kuroda. Description Language and Partitioning in Circuit Modeling for Fine Grain Dynamiically Re-configurableLogic Devices. InProc. of the 4th Meeting on Reconfigurable System, volume 2004, pages 95-102, 2004.
	In this paper, we propose a circuit construction method and a description language for Plastic Cell Architecture (PCA), a fine grained dynamically reconfigurable device. A model is divided onto several blocks with some restrictions. By using self-recon??gurability of PCA, circuit configuration changes by itself depending on formation and decomposition of blocks if needed. Moreover, each block is executed in parallel or sequentially referring to calculation resources. The proposed description language is designed by referring Haskell, one of the functional languages. This language enables flexible transformation of software into dynamically reconfigurable circuit configuration. Finally, we describe a conversion algorithm from the description language to the circuit configuration.
[kuroken-06:2004]	K. Suzuki, T. Ito, J. Kitamichi, and K. Kuroda. Design of Fast Wavelet Transform Circuits using Partial Hardware Recofiguration on PCA. In IEICE Technical Report, volume CPSY2004, pages 23-28, 2004.
	We propose architecture for the fast wavelet transform algorithm on dynamically reconfigurable devices. The architecture can change the number of inputs and parallelism. In addition, switching between forwardand inverse transforms is realized using regularity of the fast wavelet transform with only partial reconfiguration, not whole. We implemented this architecture on one of the dynamically reconfigurable devices, PCA-1.We implemented twelve circuits such as the number of inputs and parallelism, andevaluated theamount of hardware resource and the processing speeds. As a result, our proposed architecture has high flexibility for the system changing requirement.
[kuroken-07:2004]	T. Kamiyama, I. Tanaka, S. Moro, J. Kitamichi, and K. Kuroda. Proposal and Implementation of Framework for Self-Reproductive Applications on PCA. In Proc. of 25th PARTHENON Workshop, volume 2004, pages 29-35, 2004.
	This paper proposes a method to simplify designing of self-reproductive applications on an autonomous reconfigurable device, Plastic Cell Architecture (PCA). Self-reproductive applications realize distributed processing by duplication of a basic processing unit depending on optional conditions. In our proposed method, we clarify typical functions and parameters in copy/delete processes on self-reproductive applications, and design an application framework that makes designing easy by separating core application processes from reproductive functions. Designers don't need to implement self-reproduction control circuits by themselves. We applied this method to the fast Hadamard transformation circuits and we confirmed effectiveness of our method.
[kuroken-08:2004]	J. Kitamichi, C. Saito, and K. Kuroda. Extended SFL for Asynchronous System and Consideration on some Themes about it. In Proc. of 25th PARTHENON Workshop, volume 2004, pages 37-42, 2004.
	In this paper, we describe an extended method of SFL, which is one of description languages for sequential circuits to specify distributed system, asynchronous circuits, and so on in this extended language. And we discuss some themes, design and verification methods using proposed language.
[kuroken-09:2004]	S. Inoue, J. Kitamichi, and K. Kuroda. FPGA Implementation of Dynamic-Programming Algorithm for Genome Homology Analysis. In Proc. of FPGA/PLD Design Conference 2005, volume User Presentation 2005, pages 7-12, 2005.
[kuroken-10:2004]	T. Kamiyama, K. Kurata, Y. Ikehata, J. Kitamichi, and K. Kuroda. Proposal and Implementation of Framework for Self-Reproductive Applications on Dynamically Reconfigurable device PCA. In Technical Report of IEICE, volumeCPSY2004-87, pages 29-35, 2005.
	This paper proposes a method to simplify designing of self-reproductive applications on an autonomous reconfigurable device, Plastic Cell Architecture (PCA). Self-reproductive applications realize distributed processing by duplication of a basic processing unit depending on optional conditions. In our proposed method, we clarify typical functions and parameters in copy/delete processes on self-reproductive applications, and design an application framework that makes designing easy by separating core application processes from reproductive functions. Designers don't need to implement self-reproduction control circuits by themselves. We applied this method to the fast Hadamard transformation circuits and we confirmed effectiveness of our method.

Academic Activities

[kitamiti-12:2004]	Junji Kitamichi, Apr. 2003. IEEE Member
[kitamiti-13:2004]	Junji Kitamichi, Apr. 2003. Member, IPSJ
[kitamiti-14:2004]	Junji Kitamichi, Apr. 2003. Member, IEICE
[kuroken-11:2004]	Kenichi Kuroda, 2004. Member of Management Board, PARTHENON Society (NPO)

Ph.D. and Other Theses

[kitamiti-15:2004]	Kouji Ueda. Graduation Thesis: Implementation of an Out-of-Order Execution Mechanism in a MIPS Processor, University of Aizu, 2004. Thesis Advisor: Junji Kitamichi
[kitamiti-16:2004]	Mitsuhiro Honda. Graduation Thesis: Proposal of Data Structure and Algorithms for Restricted Logic with Integer Variables, University of Aizu, 2004. Thesis Advisor: Junji Kitamichi
[kitamiti-17:2004]	Syuuichi Watanabe. Graduation Thesis: Proposal of Clustering Algorithm and Implementation using FPGA for Gene Expression Profile Analysis, University of Aizu, 2004. Thesis Advisor: Junji Kitamichi
[kitamiti-18:2004]	Tomoyuki Inoue. Graduation Thesis: Implementation of compression and decompression circuits for image data on PCA, University of Aizu, 2004. Thesis Advisor: Junji Kitamichi
[kitamiti-19:2004]	Norisato Ikeda. Graduation Thesis: Evaluation of a Behavioral Synthesis Tool at System Design Level, University of Aizu, 2004. Thesis Advisor: Junji Kitamichi
[kitamiti-20:2004]	Yoshiharu Fujitsu. Graduation Thesis: An FPGA Implementation of CKY Algorithm, University of Aizu, 2004. Thesis Advisor: Junji Kitamichi
[kitamiti-21:2004]	Yutaka Watanabe. Graduation Thesis: Design and Implementation of Configurable Wavelet Transform Circuits, University of Aizu, 2004. Thesis Advisor: Junji Kitamichi
[kuroken-12:2004]	Kae Suzuki. Master Thesis: Design of Partial Reconfigurable Application Circuits for PCA- Bit-variable Divider and Wavelet Transformer -, University of Aizu, 2004.
[kuroken-13:2004]	Atsushi Suzuki. Master Thesis: Implementation of Two-step Placement and Routing Algorithm for Multi-chip Reconfigurable Devices, University of Aizu, 2004.
[kuroken-14:2004]	Ikko Tanaka. Master Thesis: Design of a Routing Management System by Virtualization on PCA, University of Aizu, 2004.
[kuroken-15:2004]	Hiroyuki Morita. Master Thesis: Study on a Dynamical Parallelism Modification Method in State Renewal for PCA Neural Network, University of Aizu, 2004.
[kuroken-16:2004]	Susumu Moro. Master Thesis: Study on Behavior Synthesis from Specifications in Functional Programming Languages for Plastic Cell Architecture, University of Aizu, 2004.
[kuroken-17:2004]	Kouji Ueda. Graduation Thesis: Implementation of an Out-of-Order Execution Mechanism in a MIPS Processor, University of Aizu, 2004.
[kuroken-18:2004]	Tomoko Ootsuka. Graduation Thesis: Implementation of Simplified Back Propagation Algorithm on a Dynamically Reconfigurable Device PCA-2, University of Aizu, 2004.
[kuroken-19:2004]	Tomoyoshi Kanno. Graduation Thesis: Implementation of a distributed resource-management module on a Self-Reconfigurable Device PCA, University of Aizu, 2004.
[kuroken-20:2004]	Yasuhiro Sugita. Graduation Thesis: Design and Implementation of a Processing Unit for Placement on a Dynamic Rconfigurable Device, University of Aizu, 2004.

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