Operating Systems Laboratory

Stanislav Sedukhin Professor	Minyi Guo Associate Professor	Hui Wang Visiting Researcher

Operating Systems Laboratory mainly researches on the following areas: Parallel computer architectures and algorithms Automatic parallelization for high performance scientific computing OS kernel/compiler integration on MIPS processor Operating systems for embedded and real-time systems Solving NP-complete problem using DNA computing Grid Computing Self-organized service environments for ELearning Parallel computer architectures and algorithms This project has two major research goals: Research of high-performance technology-scalable computer architecture; Porting and performance evaluation of the basic linear algebra, DSP, networking, and multimedia kernels on proposed and existing microprocessors. We have proposed and researched a new computer architecture (codename Trident), which consists of a set of parallel lanes (matrix engine) combined with a fast scalar core (RISC processor). Like vector architectures, each Trident lane contains a set of vector pipelines and a slice of register file. In addition to scalar registers, Trident has two types of registers to store and cyclically shift 1-D array of data within and across the parallel lanes. One key point of our architecture is the local communication within and across lanes to overcome the limitations of the future VLSI technology. Another key point is the effective processing of a mixture of 0-D (scalar), 1-D (vector), and 2-D (matrix) arrays of data, which are the fundamental data structures for many math-intensive data parallel applications. Moreover, the architecture of the Trident processor is scalable and its scalability does not require more fetch, decode, or issue bandwidth, but requires replicating the number of lanes. We have also evaluated the Trident's performance for the following kernels and algorithms: Basic Linear Algebra Subprograms (BLAS); Matrix bidiagonalization by two-sided Householder's algorithm; QR-decomposition; Tiled (blocked) algorithm for the Algebraic Path Problem; Rijndael algorithm for Advanced Encryption Standard; 2-D Discrete Cosine Transform. Some of these algorithms were ported and tested on the Intrinsity Fast MATH processor, which has a scalar MIPS processor extended with a SIMD matrix processor. Our theoretical and experimental results indicate that Trident architecture can be very useful for fast solution of many matrix-formulated problems. Automatic parallelization high performance scientific computing Irregular problems arise in computational fluid dynamics, image processing, molecular dynamics simulations, galaxy simulations, climate modeling, optimization problems, and so forth. In this research, we focused on the optimization techniques of parallelism detection and implementation on compile-time for irregular problems. We used special techniques of data dependence analysis, loop transformation, data distribution for sparse matrix, communication set generation and inter-procedural analysis. MIPS instruction simulator parallelization In the System-On-Chip age, high performance, high functional capability, and low power consumption are required for VLSI chip. In the past development methodology, functional specification of microprocessors is need to be divided into hardware function and software function. However, it has been difficult for software fengineers to understand the hardware model. When RTL system model is used for functional verification, it is possible to verify hardware functionbut it requires a lot of time for application software verification andlong development period since RTL model's simulation speed is very slow. In order to solve this problem, we design and implement a High Performance MIPS Instruction Simulator (HPMIS) based on a clustered parallel system. It can run large applicaitons on MIPS processors and evaluate the performance in parallel. Power-Aware Instruction Scheduling for embedded systems In most of compilers, the goal of traditional instruction scheduling algorithms is to improve performance interms of execution time. This can be done by some well-known ways such as superblock scheduling, hyperblock scheduling, and treegion scheduling. These scheduling strategies focus mainly on increasing performance through increasing the amount of instruction-level parallelism in program code. However, inVLIW (very long instruction word) architectures, an instruction word consists of a variable number of individual instructions. Therefore the step power and peak power consumption vary significantly depending on the parallel schedule generated by compiler. Power variation reduction without losing execution speed is an important scheduling constraint for embedded VLIW architectures. In this research, we studied some power-aware scheduling strategies for VLIWprocessors. These scheduling methods include Low power scheduling for basic blocks with integer programming Modulo and Software Pipelining for loops Register allocation and cache reuse for power reduction. Solving NP-complete problem using DNA computing Nowadays, producing roughly 10 8DNA strands that fit in a test tube is possible through advances in molecular biology. Adleman proposed the first paper in which it is shown that each DNA strand (DeoxyriboNucleic Acid) could be employed towards calculating solutions to an instance of the NP-complete Hamiltonian path problem (HPP) with seven vertices. Lipton demonstrated that using Adleman's experiment determines solutions to an instance of the NP-complete satisfiability (SAT) problem. Therefore, the Adleman-Lipton model seems to be another selection of solving NP-complete problem. In this research, we focused on developing DNA algorithms in the Adleman-Lipton model for resolving 3-DIMENSIONAL MATCHING (3DM), andMINIMUMSET-COVER (transformation from 3DM). Alsowe focused on developing simulator to simulate real DNA experiment of the proposed algorithms. Grid and P2P Computing The grid is an emerging infrastructure that will fundamentally change the way we think about - and use - computing. The grid will connect multiple regional and national computational grids to create a universal source of computing power. A Grid is a computing and data handling virtual system formed by aggregating the diverse services provided by distributed resources to synthesize problem solving environments. Some of the issues in Grid architecture are: (a) supporting adaptability, extensibility, and scalability, (b) allowing systems with different administrative policies to inter-operate while preserving site autonomy, (c) coallocating resources, and (d) supporting quality of service. In Operating Systems Lab, in the second stage of our GridOS research in 2004, we researched and developed a service-oriented P2P architecture for grid computing, called JXTPIA system. The JXTPIA system provides the basic functionalities for Grid computing, such as resource allocation, task scheduling, task assignment, network structure constructing and maintenance, and data sharing. One of the main challenges in developing the JXTPIA system is efficient allocation of resources and assignment of a variety of tasks issued by users. We devise, test, and evaluate new algorithms for resource allocation and task assignment to improve the efficiency of the JXTPIA system. Self-organized Service Environments for ELearning Nowadays eLearning become more and more popular in modern education service. However, traditional eLearning systems are content basedand usually employ client/server paradigm for service providing. With such a paradigm, the overall capability of the system is constrained by the server's performance. Hence, the scalability becomes one of the key problems to be addressed. Although server-based approaches such as clustering, grid computing could enlarge service capability, its cost is expensive and cannot satisfy with the ever-increasing user requirement. IP multicast has been considered as another efficient way for this problem, but till now, its large-scale deployment is inhibited by both technical and non-technical factors. In fact, there is an explosive growth in the desktop computing capability in the past several years. And current research effects on P2P computing and its successful applications show that these resources could play important roles in distributed computing scenario. We deem P2P computing is the emerging architecture that seems to be the key enablers to the new eLearning model. And our motivation of the self-organized service environment for eLearning is to provide interactive educational services to a large number of users located at universities, offices or at their homes through harnessing the available resource among the participating nodes. The primary goal of this project is to offer a widely and broadly accessible eLearning environment to all the interested audiences in a more economic and efficient way without introducing additional complexity. We design andimplement a self-organized service system for eLearning. It is important to be mentioned that our focus of this environment is on the architecture and delivery techniques employed for ensuring live stream service in a scalable way as well as supporting interaction.

Refereed Journal Papers

[hwang-01:2004]	H. Wang, M. Guo, and D. Wei. A Parallel Implementation of Multi-Domain High-Order Navier-Stokes Equations Using MPI. IEICE Trans. Info. and Sys., E87-D(7):1759-1765, 2004.
	In this paper, Message Passing Interface (MPI) techniques are used to implement high-order full 3-D Navier-Stokes equations in multi-domain applications. A two-domain interface with five-point overlapping used previously is expanded to a multi-domain computation. There are normally two approaches for this expansion. One is to break up the domain into two parts through domain decomposition (say, one overlapping), then use MPI directives to further break up each domain into n parts. Another is to break the domain up into 2n parts with (2n - 1) overlappings. In our present effort, the latter approach is used and finite-size overlappings are employed to exchange data between adjacent multi-dimensional sub-domains. It is an alternativeway to parallelize the high-order full 3-D Navier-Stokes equations into multi-domain applications without adding much complexity. Results with high-order boundary treatments show consistency among multi-domain calculations and single-domain results.
[hwang-02:2004]	H. Wang, M. Guo, and D. Wei. A Divide-and-Conquer Algorithm for Irregular Redistribution in Parallelizing Compilers. Journal of Supercomputing, 29(2):157-170, 2004.
	In order to achieve higher load balancing, it is necessary to solve irregular block redistribution problems, which are different from regular block-cyclic redistribution. High Performance Fortran version 2 (HPF-2) provides irregular distribution functionalities, such as GEN_ BLOCK and INDIRECT. This paper is devoted to develop an efficient algorithm that attempts to obtain near optimal scheduling while satisfying the conditions of minimal message size of total steps and the minimal number of steps for irregular array redistribution. The algorithm intends to decrease the computation costs by dividing the whole block into sub-blocks and solving the sub-problems accordingly, and then merging them together to get final results. Simulation results show that our algorithm has comparable performance with a relocation algorithm developed previously (H. Yook and M. Park. Proceedings of the IASTED International Conference Parallel and Distributed Computing and Systems, Nov. 3-6, MIT, Boston, USA, 1999).
[minyi-01:2004]	Minyi Guo, Michael Ho, and Weng-Long Chang. Fast parallel molecular solution to the dominating-set problem on massively parallel bio-computing. Parallel Computing, 30(9):1109-1125, 2004.
	This paper shows how to use DNA strands to construct solution space of molecules for the dominating-set problem and how to apply biological operations to solve the problem from the solution space of molecules. In order to achieve this, we have proposed some DNA based parallel algorithms using the operations in Adleman-Lipton model, together with the analysis of the computational complexity for DNA parallel algorithms.
[minyi-02:2004]	Weng-Long Chang, Minyi Guo, and Michael Ho. Towards Solution of the Set-splitting Problem on Gel-based DNA Computing. Future Generation Computer Systems, 20(5):875-885, 2004.
	Adleman wrote the first paper that demonstrated that DNA (Deoxyribo Nucleic Acid) strands could be applied for dealing with solutions of the NP-complete Hamiltonian path problem (HPP). Lipton wrote the second paper that showed that the Adleman techniques could also be used to solve the NP-complete satisfiability (SAT) problem (the first NP-complete problem). Adleman and his co-authors proposed sticker for enhancing the Adleman-Lipton model. In this paper, it proves how to apply sticker in the sticker-based model to construct solution space of DNA in the set-splitting problem and how to apply DNA operations in the Adleman-Lipton model to solve that problem from the solution space of sticker.
[minyi-03:2004]	Minyi Guo. Preface of Special Issue on Parallel and Distributed Computing with Applications. Journal of Supercomputing, 29(2):123-124, 2004.
	In this paper, we give an overview of the recent important advances in the area of parallel and distributed computing and applications. We introduce some recent achievements in the scientific and engineering computing domains
[minyi-04:2004]	Hui Wang, Minyi Guo, and Daming Wei. Divide-and-conquer Algorithm for Irregular Redistributions in Parallelizing Compilers. Journal of Supercomputing, 29(2):157-170, 2004.
	In order to achieve higher load balancing, it is necessary to solve irregular block redistribution problems, which are different from regular block-cyclic redistribution. High Performance Fortran version 2 (HPF-2) provides irregular distribution functionalities, such as GENBLOCK and INDIRECT. This paper is devoted to develop an efficient algorithm that attempts to obtain near optimal scheduling while satisfying the conditions of minimal message size of total steps and the minimal number of steps for irregular array redistribution. The algorithm intends to decrease the computation costs by dividing the whole block into sub-blocks and solving the sub-problems accordingly, and then merging them together to get final results. Simulation results show that our algorithm has comparable performance with a relocation algorithm developed previously (H. Yook and M. Park. Proceedings of the IASTED International Conference Parallel and Distributed Computing and Systems, Nov. 3, 1999).
[minyi-05:2004]	Hui Wang and Minyi Guo. A Parallel Implementation of Multi-domain High-order Navier-Stokes Equations Using MPI. IEICE Transactions on Information and Systems, E87-D(7):1759-1765, 2004.
	In this paper, Message Passing Interface (MPI) techniques are use to implement high-order full 3-D Navier-Stokes equations in multi-domain applications. A two-domain interface with five-point overlapping used previously is expanded to a multi-domain computation. There are normally two approaches for this expansion. One is to break up the domain into two parts through domain decomposition (say, one overlapping), then using MPI directives to further break up each domain into n parts. Another is to break the domain up into 2n parts with (2n - 1) overlappings. In our present effort, the latter approach is used and finite-size overlappings are employed to exchange data between adjacent multi-dimensional sub-domains. It is an alternativeway to parallelize the high-order full 3-DNavier-Stokes equations into multi-domain applications without adding much complexity. Results with high-order boundary treatments show consistency amongmulti-domain calculations and single-domain results.
[minyi-06:2004]	Michael Ho, Weng-Long Chang, and Minyi Guo. Fast Parallel Solution For Set-Packing and Clique Problems by DNA-based Computing. IEICE Transactions on Information and Systems, E-87D(7):1782-1788, 2004.
	This paper shows how to use sticker to construct solution space of DNA for the library sequences in the set-packing problem and the clique problem. Then, with biological operations, we propose DNA-based algorithms to remove illegal solutions and to find legal solutions for the set-packing and clique problems from the solution space of sticker. Any NP-complete problem in Cook's Theorem can be reduced and solved by the proposed DNA-based computing approach if its size is equal to or less than that of the set-packing problem. Otherwise, Cook's Theorem is incorrect on DNA-based computing and a new DNA algorithm should be developed from the characteristics of the NP-complete problem. Finally, the result to DNA simulation is given.
[minyi-07:2004]	Fan Chan, Jiannong Cao, Alvin T.S. Chan, and Minyi Guo. Programming Support for MPMD Parallel Computing in Cluster GOP. IEICE Transactions on Information and Systems, E-87D(7):1693-1702, 2004.
	Many parallel applications involve different independent taskswith their own data. Using the MPMD model, programmers can have a modular view and simplified structure of the parallel programs. Although MPI supports both SPMD and MPMD models for programming. MPI libraries do not provide an efficient way for task communication for the MPMD model. We have developed a programming environment, called ClusterGOP, for building and developing parallel applications. Based on the graph-oriented programming (GOP) model, ClusterGOP provides higher-level abstractions for message-passing parallel programming with the support of software tools for developing and running parallel applications. In this paper, we describehow ClusterGOP supports programming of MPMD parallel applications on top of MPI. We discuss the issues of implementing the MPMD model in ClusterGOP using MPI and evaluate the performance by using example applications.
[minyi-08:2004]	Minyi Guo, Weng-Long Chang, and Jiannong Cao. Using Sticker to Solve the 3-Dimensional Matching Problem in Molecular Supercomputers. International Journal of High Performance Computing and Networking, 1(1):128-139, 2004.
	Adleman demonstrated that DNA (Deoxyribonucleic acid) strands could be applied for dealingwith solutions toan instance of the NP-complete Hamiltonian path problem (HPP) (Adleman, 1994). The Adleman techniques could also be used to solve the NP-complete satisfiability (SAT) problem (the first NP-complete problem). Furthermore, sticker is used for enhancing the Adleman-Lipton model. In this paper, we first use sticker to construct solution space of DNA library sequences for the 3-dimensional matching problem. Then, in the Adleman-Lipton model, we propose an algorithm to remove illegal solution and find legal solution for the 3-dimensional matching problem from solution space of sticker. Finally, a simulation result for our algorithm is generated.

Referred Proceeding Papers

[hwang-03:2004]	H. Wang, M. Guo, andD.Wei. Effcient List Algorithms for Irregular Block Redistribution inParallelizing Compilers. In Editor D.Wei, editor, Proc. of The Fourth Int. Conf. on Computer and Information Technology (CIT 2004), pages 467-472, Wuhan, China, Sept. 2004. Wuhan University, IEEE Computer Society Press.
	In parallelizing compilers on distributed memory systems, distributions of irregular sized array blocks are provided for load balancing and irregular problems. The irregular redistribution is different from the regular block-cyclic redistribution. This paper is devoted to developing algorithms for irregular redistribution that attempt to obtain near optimal scheduling while satisfying the minimal communication costs condition and the minimal step condition. Efficient algorithms are developed and their experimental results are compared. One improved list algorithm provides more chance for conflict messages in its relocation phase. It allocates conflict messages through methods used in a divide-and-conquer algorithm and a relocation algorithm proposed previously. The method of selecting the smallest relocation cost guarantees that the improved list algorithm is more efficient than others in average.
[minyi-09:2004]	Minyi Guo, Weng-Long Chang, and Jiannong Cao. The Noncontinuous Direction Vector I Test. In Proceedings of 7th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2004), Hong Kong, China, May 2004. IEEE Computer Society Press.
[minyi-10:2004]	Weng-Long Chang, Minyi Guo, and Machael Ho. Fast Parallel Molecular Algorithms for DNA-based Computation: Factoring Integers. In Proceedings of the 4th IEEE Symposium on Bioinformatics and Bioengineering (BIBE 2004), Taichung, Taiwan, May 2004. IEEE Computer Society Press.
[minyi-11:2004]	Minyi Guo and Weng-Long Chang. Multi-dimensional Interval I Test with Induction Variables in Array References. In Proceedings of the PARA'04 Workshop on State-of-the-art Scientific Computing, Copenhagen, Denmark, June 2004. University of Demank, Springer.
[minyi-12:2004]	Son-Hong Ngo, Xiaohong Jiang, Susumu Horiguchi, and Minyi Guo. Dynamic Routing and Wavelength Assignment in WDM Networks with Ant-Based Agents. In Proceedings of the 2004 International Conference on Embedded and Ubiquitous Computing, Aizu-Wakamatsu, Japan, August 2004. Information Processing Society of Japan, Springer. Lecture Notes in Computer Science 3207
[minyi-13:2004]	Jiannong Cao, Kwok Ming Chan, Geofffrey Yu-Kai Shea, and Minyi Guo. Location-aware Information Retrieval for Mobile Computing. In Proceedings of the 2004 International Conference on Embedded and Ubiquitous Computing, Aizu-Wakamatsu, Japan, August 2004. Information Processing Society of Japan, Springer. Lecture Notes in Computer Science 3207
[minyi-14:2004]	Tiecheng Gu, Baoliu Ye, Minyi Guo, and Daoxu Chen. Implementing Cooperative Caching in a Distributed Streaming Server Cluster. In Proceedings of the 2004 International Conference on Embedded and Ubiquitous Computing, Aizu-Wakamatsu, Japan, August 2004. Information Processing Society of Japan, Springer. Lecture Notes in Computer Science 3207
[minyi-15:2004]	Ke Li, Minyi Guo, and Li Li. Switching Cost, Market Effects and the Pricing Model of e-Commerce. In Proceedings of the 2004 International Conference on Service Computing (SCC-04), Shanghai, China, September 2004. IEEE Computer Society, IEEE CS Press.
[minyi-16:2004]	Stephen Pellicer, Yi Pan, and Minyi Guo. Distributed MD4Password Hashing with Grid Computing Package BOINC. In Proceedings of the 2004 International Conference on Grid and Cooperative Computing (GCC-04), Wuhan, China, September 2004. Computer Society of China, Springer. Lecture Notes in Computer Science 3251
[minyi-17:2004]	Vinh Trong Le, Son Hong Ngo, Xiaohong jiang, Susumu Horiguchi, and Minyi Guo. A Genetic Algorithm for Dynamic Routing and Wave length Assignment in WDM Networks. In Proceedings of the 2nd International Conference on Parallel and Distributed Processing and Applications(ISPA-04), Hong Kong, China, December 2004. IEEE Hong Kong Chapter, Hong Kong Polytechnic Univ., Springer. Lecture Notes in Computer Science 3358
[sedukhin-01:2004]	A. Takahashi and S. Sedukhin. Tiled Parallel Algorithm for the Algebraic Path Problem on advanced SIMD Processors. In Editor Trystram, D., editor, Proceedings of the 3rd International workshop on Parallel Matrix Algorithms and Applications (PMAA'04), pages 59-64, MARSEILLE Cedex 09,France., Oct. 2004. Centre International de Rencontres Mathematiques (CIRM), France, CIRM.
	The paper presents an efficient tiled parallel algorithm for the Algebraic Path Problem (APP). It is known that the complexity of the APP is the same as that of the classical matrix-matrix multiplication; however, the solution of the APP takes much more running time because of its unique data dependencies that limits data reuse drastically. We examine a tiled parallel implementation of the APP on the Intrincity FastMATH processor, which consist of a scalar MIPS processor extended with a SIMD matrix coprocessor. The matrix coprocessor supports native matrix instructions on an array of 4x4 processing elements. Our experimental results show a peak performance of 9.27 GOPS (Giga Operations per second) on the FastMATH processor. This performance was achieved due to reduced processor-memory data traffic by data reuse and effective parallel data processing by native matrix instructions. Findings from our experimental results indicate that the matrix SIMD extension to (super)scalar processor will be useful for fast solution of many matrix-formulated problems.
[sedukhin-02:2004]	S. Sedukhin and M. Soliman. A Technology-Scalable Matrix Processor for Data Parallel Applications. In Editor Yoshio Oyanagi, editor, The 7th International Conference on High Performance Computing and Grid in Asia Pacific Region (HPCAsia 2004), Poster Session, pages 49-50, Tokyo, Japan, July 2004. IPS of Japan, IPS of Japan.
	This paper discusses the physical and technological limitations of today and future VLSI technology and proposes the Trident processor architecture which is based on local communications. Trident is a research processor, which consists of a set of parallel lanes combined with a fast scalar core. Like vector architectures, each Trident lane contains a set of vector pipelines and a slice of register file. However, Trident has two types of registers to store and cyclically shift 1-D array of data within and across the parallel lanes. One key point of our architecture is the local communication within and across lanes to overcome the limitations of the future VLSI technology. Another key point is the effective processing of a mixture of 0-D (scalar), 1-D (vector), and 2-D(matrix) arrays of data, which are the fundamental data structures for data parallel applications. Moreover, the architecture of the Trident processor is scalable and its scalability does not require more fetch, decode, or issue bandwidth, but requires replicating the number of lanes. This paper describes the main features of the Trident processor and evaluates its performance on the QR factorization algorithm.

Books

[hwang-04:2004]	Peng Z. Kara A. Wei D., Wang H. and He Y. (Eds.). Proc. of The 4th Int. Conf. on Computer and Information Technology. IEEE CS Press, Los Alamitos, California, 2004.
[minyi-18:2004]	Jiannong Cao, Laurence T. Yang, Minyi Guo, and Francis Lau. Parallel and Distributed Computing with Applications. Number 3358 in Lecture Notes in Computer Science. Springer-Verlag, Berlin, 2004.
[minyi-19:2004]	Laurence T. Yang, Minyi Guo, Guang R. Gao, and Niraj K. Jha. Embedded and Ubiquitous Computing. Number 3207 in Lecture Notes in Computer Science. Springer-Verlag, Berlin, 2004.

Grants

[minyi-20:2004]

Minyi Guo. The Telecommunication Advancement Foundation, 2003-2004.

Academic Activities

[hwang-05:2004]	H. Wang, 2004. Member of the Program Committee of The 1st International Workshop on Performance Modelling in Wired, Wireless, Mobile Networking and Computing
[hwang-06:2004]	H. Wang, 2004. Member of the Program Committee of The Second International Symposium on Parallel and Distributed Processing and Applications, Hong Kong
[hwang-07:2004]	H. Wang, 2004. Publication Chair of The 2004 International Conference on Embedded And Ubiquitous Computing, Japan
[hwang-08:2004]	H. Wang, 2004. Co-Chair of the Program Committee of The 4th International Conference on Computer and Information Technology, China
[hwang-09:2004]	H. Wang, 2004. Guest Editor-in-Chief of The International Journal of Pervasive Computing and Communications, UK
[hwang-10:2004]	H. Wang, 2005. Guest Editor/Coordinator of The IEICE Transaction on Information and Systems, Japan
[hwang-11:2004]	H. Wang, 2005. Publicity Chair of The 2005 International Conference on Embedded And Ubiquitous Computing, Japan
[hwang-12:2004]	H. Wang, 2005. Publication Chair of The Third International Symposium on Parallel and Distributed Processing and Applications, China
[hwang-13:2004]	H. Wang, 2005. Chair of OC/PCMember of The 4th International Workshop on Databases in Networked Information Systems, Japan
[hwang-14:2004]	H. Wang, 2005. Member of the Program Committee of The 6th Workshop on Parallel and Distributed Scientific and Engineering Computing, USA
[hwang-15:2004]	H. Wang, 2005. Member of the Program Committee of The First International Workshop on Ubiquitous Smart Worlds, Taiwan
[minyi-21:2004]	Minyi Guo, 2002-. Member, IEICE
[minyi-22:2004]	Minyi Guo, 2000-. Member, IEEE Computer Society
[minyi-23:2004]	Minyi Guo, 2000-. Member, ACM
[minyi-24:2004]	Minyi Guo, 1995-. Member, IPSJ
[minyi-25:2004]	Minyi Guo, December 2004. General Chair, The 2004 International Symposium on Parallel and Distributed Computing with Applications (ISPA2004).
[minyi-26:2004]	Minyi Guo, August 2004. General Chair, the 2005 International Conference on Embedded and Ubiquitous Computing
[minyi-27:2004]	Minyi Guo, March 2004. Workshop Chair, the 1st International Workshop on Embedded Computing (ICDCS-EC04).
[minyi-28:2004]	Minyi Guo, March 2005. Program Committee Member, The 19th International Parallel and Distributed Processing Symposium (IPDPS 2005)
[minyi-29:2004]	Minyi Guo, October 2004. Program Committee Member, The International Workshop on Grid and Cooperative Computing (GCC 2004)
[minyi-30:2004]	Minyi Guo, October 2004. Program Committee Member, The 2004 IFIP International Conference on Network and Parallel Computing (NPC 2004)
[sedukhin-03:2004]	S Sedukhin, Apr. 2004. IEEE CS, member
[sedukhin-04:2004]	S Sedukhin, Apr. 2004. ACM, member
[sedukhin-05:2004]	S Sedukhin, Apr. 2004. IASTED Technical Committee on Parallel Processing, Member
[sedukhin-06:2004]	S Sedukhin, Apr. 2004. International Journal of Neural, Parallel & Scientific Computations, Member of the Editorial Board
[sedukhin-07:2004]	S Sedukhin, Apr. 2004. International Journal of Parallel Processing Letters, Member of the Editorial Board
[sedukhin-08:2004]	S Sedukhin, Sept. 2004. The Eighth Asia-Pacific Computer Systems Architecture Conference (ACSAC004), Stearing & Program Committee Member
[sedukhin-09:2004]	S Sedukhin, Aug. 2004. 6th International Conference on Parallel and Distributed Computing, Applications, and Technologies (PDCAT 2002), Program Committee Member
[sedukhin-10:2004]	S Sedukhin, Feb. 2005. International Conference on Parallel and Distributed Computing and Networks, Program Committee Member
[sedukhin-11:2004]	S Sedukhin, June. 2005. The 2005 High Performance Computing & Simulation (HPC&S) Conference, Program Committee Member
[sedukhin-12:2004]	S Sedukhin, May. 2005. Eighth International Conference on Pattern Recognition and Information Processing (PRIP'2005, Program Committee Member

Ph.D. and Other Theses

[minyi-31:2004]	Yoshihiro Saitoh. Master Thesis: Design, Implementation and evaluation of a P2P sysmtes based on JXTA, University of Aizu, 2004. Thesis Advisor: Minyi Guo.
[minyi-32:2004]	Kenichi Sumitomo. Graduation Thesis: Task Assignation on Open Peer-to-Peer Network Systems, University of Aizu, 2004. Thesis Advisor: Minyi Guo.
[minyi-33:2004]	Manabu Morita. Graduation Thesis: The Implementation of an OS for Game Boy Advance, University of Aizu, 2004. Thesis Advisor: Minyi Guo.
[minyi-34:2004]	Takato Izaiku. Graduation Thesis: Deploy Task Sources Effects on a P2P Networking System, University of Aizu, 2004. Thesis Advisor: Minyi Guo.
[minyi-35:2004]	Takamasa Oono. Graduation Thesis: Performance Evaluation for P2P Tool JXTPIA, University of Aizu, 2004. Thesis Advisor: Minyi Guo.
[minyi-36:2004]	Hiroaki Kobayashi. Graduation Thesis: Development of a RT Linux Sistribution on SuperH4, University of Aizu, 2004. Thesis Advisor: Minyi Guo.
[minyi-37:2004]	Yukinori Sakuratani. Graduation Thesis: Parallel Processing on Comparison of DNA Sequences, University of Aizu, 2004. Thesis Advisor: Minyi Guo.
[sedukhin-13:2004]	Mostafa Soliman. PhD Thesis: A Technology-Scalable Matrix Processor for Data Parallel Applications, University of Aizu, 2004. Thesis Advisor: Sedukhin, S.
[sedukhin-14:2004]	Masayoshi Oouchi. Graduation Thesis: Implementation and Evaluation of the DCT/IDCT Algorithm on the Trident Simulator, University of Aizu, 2005. Thesis Advisor: Sedukhin, S.
[sedukhin-15:2004]	Koichi Midorikawa. Graduation Thesis: An Implemenation of the AES on the FastMATH Processor, University of Aizu, 2005. Thesis Advisor: Sedukhin, S.
[sedukhin-16:2004]	Shuuichi Kojima. Graduation Thesis: Performance Evaluation of the 2-D DCT on the Intrinsity FastMATH Processor, University of Aizu, 2005. Thesis Advisor: Sedukhin, S.
[sedukhin-17:2004]	Yuji Kobayashi. Graduation Thesis: Educational Java Applet for Floyd-Warshall Algorithm, University of Aizu, 2005. Thesis Advisor: Sedukhin, S.
[sedukhin-18:2004]	Masafumi Yamada. Master Thesis: SSE solutions for the Algebraic Path Problem, University of Aizu, 2005. Thesis Advisor: Sedukhin, S.

Others

[minyi-38:2004]	Minyi Guo. Editor in Chief, International Journal of Embedded Systems
[minyi-39:2004]	Minyi Guo. Editor, Journal of Embedded Computing
[minyi-40:2004]	Minyi Guo. Editor, International Journal of Web and Grid Services
[minyi-41:2004]	Minyi Guo. Editor, International Journal of High Performance Computing and Networking
[minyi-42:2004]	Minyi Guo. Editor, International Journal of Computer and Applications
[minyi-43:2004]	Minyi Guo. Editor, Journal of Pervasive Computing and Communications
[minyi-44:2004]	Minyi Guo. Guest Editor-in-Chief, Special issue on Hardware/Software Support for High Performance Scientific and Engineering Computing of IEICE Transactions on Information and Systems
[minyi-45:2004]	Minyi Guo. Guest Editor, Special on Parallel and Distributed Processing with Applications of Journal of Supercomputing

2006 THE UNIVERSITY OF AIZU ALL RIGHTS RESERVED