Computer Devices Laboratory

Kazuyuki Saito Professor	Yasuhiro Hisada Assistant Professor

The Computer Device Laboratory (CDL) focuses on education and research on VLSI technologies, devices, and their related area. Education: For the undergraduate students; Physics of Semiconductor Devices (K. Saito) Principles of VLSI Devices and Process Technologies (K. Saito) Japanese Writing (K. Saito) Information and Industries (K. Saito) Introduction to Programming (Y. Hisada) Electronic Circuits (Y. Hisada) For the graduate students ULSI Technologies (K. Saito) Research: The main objectives of the research in CDL are to develop new environment for VLSI design, diagnoses, and manufacturing. These will be an intelligent manufacturing of VLSIs including a statistical representation, a physical representation, and an expert system representation of the environments. The objects of representations are not restricted in the devices and physical technologies, but will cover from the manufacturing system modeling to the yield enhancement and reliability of VLSI. Currently, a new system to estimate resources for the semiconductor manufacturing has developed. The system has been used in the semiconductor companies for monthly planning of their human and machinery resources. In addition a novel dispatching algorithm for the mixed LSI production is developed. The mixed production is inevitable in the system LSI fabrication. The new dispatching algorithm, named pseudo periodical priority dispatching, is superior to FCFS in setup frequency, and in response time, and to SPT in tardiness. Therefore, the algorithm will be promising to reduce the cost in the future semiconductor manufacturing. Research Projects have been performed in CDL are as follows: Research on the Product-mix VLSI Manufacturing (Grant-In-Aid For Scientific Research) Low Power VLSI Technologies New Dispatching Method for VLSI Manufacturing Manufacturing System Modeling and Simulation Tool based on Petri Net Optimization of Resources for VLSI Production (with Fujitsu Tohoku Electronics) Wavelet Analyses on the Electrocardiogram (with Fukushima Medical University) A new Approach for Logic Design (with Fujitsu Tohoku Electronics) Cooperative Co-evolutionally Hardware and its Application (Grant-In-Aid for Scientific Research) Research on Parameter Extraction for VLSI Simulation (with NTT Laboratories) Research on Defect Analysis of the Implanted Silicon Layer (with NTT Laboratories)

Refereed Proceeding Papers

[k-saito-01:2005]

Sumika Arima, Kazuyuki Saito, and Ushio Sumita. Development of Resource Planning and Execution Management System for a Closed Loop SCM. In The 5th workshop on Business Aspect of Closed-Loop Supply Chains, 2005.

One of important problem in a "Closed loop model" is that not only a forward product flow but also a reverse product flow [1] should be considered for an accurate estimation of resource plan and an execution management of processing steps, however, the reverse flow is not expected and only just detected empirically as the result, and so that is difficult to plan and manage. The problem is to be solved by an extension model for a planning system and an execution management system, and their collaboration. What to consider in planning is an accurate estimation model considering the rework workload to each processing step. What to consider in execution management is monitoring and forecasting WIP(Work-In-Process) includes reworks and making dynamic decision of the WIP management with considering available to promise of a planned due date, maximization of processing step utilization, and so on. Here the key point to consider a closed loop model is a collaboration of the planning and the execution systems with interactive information management and a strategic unified operation model like an algorithm introduced in this paper. For accurate, operational, and executive planning and its execution, the planning system use execution results such as WIP arrivals and service histories, and the execution system use planned information such a due date (response time).

Academic Activities

[k-saito-02:2005]

Kazuyuki Saito, 2006. IEEE Sendai Section, member of Executive Committee

Ph.D and Other Theses

[hisada-01:2005]	Akihiro Ishida. Graduation Thesis: Development of Telecare System using a Network, University of Aizu, 2005. Thesis Advisor: Y. Hisada
[hisada-02:2005]	Yu Kamiguchi. Graduation Thesis: A Method of Analysis using Wavelet Transform for ECG, University of Aizu, 2005. Thesis Advisor: Y. Hisada
[hisada-03:2005]	Yousuke Suzuki. Graduation Thesis: Control of HID Class for USB Interface, University of Aizu, 2005. Thesis Advisor: Y. Hisada
[k-saito-03:2005]	Masanori Kudo. Graduation Thesis: Research on the Feature Extraction of the Japanese Article Using Text Mining, University of Aizu, 2006. Thesis Advisor: Kazuyuki Saito
[k-saito-04:2005]	Mamoru Techikawahara. Graduation Thesis: Modeling Based on Colored Timed Petri Net to Simulate Manufacturing of Mixed Products, University of Aizu, 2006. Thesis Advisor: Kazuyuki Saito
[k-saito-05:2005]	Kouichi Watanabe. Graduation Thesis: A Study on Single-ended Pass-transistor Logic (SPL) using SPICE, University of Aizu, 2006. Thesis Advisor: Kazuyuki Saito

2007 THE UNIVERSITY OF AIZU ALL RIGHTS RESERVED