Computer Education Laboratory

Kenichi Kuroda Professor	Junji Kitamichi Associate Professor	Yuichi Okuyama Assistant Professor

The academic area of the laboratory mainly covers computer design methodology. Educational course design for VLSI design, formal verification and reconfigurable computing are the major themes of this lab. Education: We have been developing an education program of VLSI design based on VDEC (VLSI Design and Education Center) support. VDEC offers various kinds of design tools without license costs and accepts chip fabrication orders in low price. This program was started as a joint research with Prof. Shima, who left from this university in 2004, in Computer Architecture Laboratory in 2001. Web-based manuals for HDL design, verification, and layout tools have been developed and are being updated depending on VDEC support tools every year. This year, we have been collaborating with Prof. Miyazaki who joined this university from April, 2005 at Computer Organization Lab. This spring, we welcomed Prof. Okuyama from NTT Network Innovation Laboratories. He graduated from this university and joined NTT in 2002. He is now dedicating himself to education and research as a young faculty member. In 2005, members of our laboratory are three professors, 2 doctoral program students, 14 master program students, and 8 graduate thesis students. Among the above students, one withdrew and got job, one entered the graduate school of other university and 12 students got jobs after graduation. Research: We have been proceeding the joint research with NTT Network Innovation Laboratories on ?Library Modules Development for Dynamically Reconfigurable Devices, PCA (Plastic Cell Architecture)? since 2003. Various kinds of circuits based on PCA (one of dynamically reconfigurable devices) have been designed and implemented. For high productivity, library modules, similar to the standard cell libraries in the conventional VLSI design technology, have been developed and applied to applications for parallel processors, neural networks, and image compression. The Joint research with NTT has been carried out. Some of the results were published and presented at conferences. As to the traditional synchronous circuit technology, various applications such as bio-informatics and network security have been surveyed based on VDEC technology environment. Members of the Computer Education Laboratory Prof. Kenichi Kuroda: Before his coming to this university, he belonged to the NTT laboratories and he was engaged with the research on superconductor devices, SAW devices, and X-ray optics. He joined this university mid 1995. He received his Dr. Eng. from Tokyo University in 1991. He had been a member of the Computer Device Lab for 5 years and moved to this lab in summer 2000. After coming to this university, he was interested in VLSI design technology. Especially, dynamically reconfigurable devices such as PCA (Plastic Cell Architecture) are the current major research direction. Prof. Junji Kitamichi: He received the B.S. and Ph.D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Center at Osaka University, where he was assistant Professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. His research interests include formal methods for VLSI design, design verification, hardware description language, dynamical reconfigurable architectures, and real-time systems. Prof. Yuichi Okuyama: He was born in 1975. He received the M.S and Ph.D degrees in computer science and engineering from the University of Aizu in 1999 and 2002, respectively. He entered NTT Network Innovation Laboratories and was engaged with the development of PCA (Plastic Cell Architecture) devices. He joined the University of Aizu in 2005 as an assistant professor. His current interests are implementation of applications and tools for design automation on reconfigurable device(FPGA and other devices) and design of hardware for scientific calculations. Students : Research Topics Doctor Program Toshiyuki Ito : Processors on dynamically reconfigurable device PCA. Keigo Kurata : Artificial neural networks on PCA. Master Program : PCA related topics Yoshuke Ikehata, Hironori Endo, Tomoki Kamiyama, Tomoko Otsuka, Tomoyosi Kanno, Yasuhiro Sugita. Master Program : Application circuits and tool development Kenji Asano, Sou Inoue, Junichi Nakajima, Chizuru Saito, Hiroaki Tanba, Mitsuhiro Honda, Koji Ueda, Shuichi Watanabe. Graduation Thesis Students : PCA related topics Shinya Iwazaki, Natsuki Chubachi, Kazuya Yokohari, Kazuya Misho. Graduation Thesis Students : Application circuits and tool development Jun Muraoka, Kimiyosi Muromoto, Noriaki Kaida, Hajime Katayama.

Refereed Proceeding Papers

[kitamiti-01:2005]	H. Tanba, Y. Yamada, J. Kitamichi, and K. Kuroda. Hardware implementations of high-speed network monitors. In 2005 IEEE VLSITSA International Symposium on VLSI Design, Automation & Test, pages 33-36. IEEE, Apr. 2005.
	Recently, many kinds of malicious attacks on the Internet such as Denial of Service (DoS) attacks are increasing, and many unnecessary packets waste network resources. Network monitors to watch and filtering these unnecessary packets have been proposed. However, in the present network monitors implemented using several servers and monitoring software, it will be difficult to watch in real time and remove unnecessary packets at the very high-speed backbone network such as intercontinental one. One of the methods to realize a real time network monitor is an implementation by the hardware. Therefore, in this research, we propose a hardware architecture that detects IP flooding and SYN Flood; these are kinds of DoS attacks. We design the hardware circuits in ASIC and FPGA. As the results of logic synthesis, we confirm that these detection circuits can work on the high-speed traffic such as more than 10 millions packets/sec.
[kitamiti-02:2005]	S. Watanabe, J. Kitamichi, K. Kuroda, and Y. Takenaka. Proposal of Clustering Algorithm and Implementation using FPGA for Gene Expression Profile Analysis. In The 18th Workshop on Circuits and Systems in Karuizawa, pages 187-192. IEICE, Apr. 2005.
	This paper describes a clustering hardware algorithm based on a p - quasi complete graph structure for gene expression profile analysis and its implementation on an FPGA device. The problem presented in this paper is based on the maximum p - quasi complete subgraph problem, which is known to be NP-complete. The proposed algorithm refers to a binary Hopfield neural network for the realization of parallel processing. The proposed architecture has some noteworthy features. For example, the circuit has high scalability by the simplicity of placement of modules and routing between modules using a ring network. If the number of vertices of a graph is 256, then the hardware implementation of the proposed method using FPGA can execute the proposed algorithm about 90 times as fast as the software implementation on a general-purpose computer.
[kitamiti-03:2005]	K. Asano, J. Kitamichi, and K. Kuroda. Proposal of a System Level Simulation Method for Dynamically Reconfigurable Architecture with Dynamic Generation and Elimination of Modules. In Design Automation Symposium 2005, pages 7-12. IPSJ, Aug. 2005.
	In this paper, we propose a system level simulation method for dynamically reconfigurable architectures. The method utilizes SystemC as system level language, and dynamic process is used to realize the generation and the elimination of modules. The proposed functions are impremented as the class library, so we can describe simulation model easily. We describe an example model, first hadamard transform algorithm, using our proposed method, and show the results.
[kuroken-01:2005]	Toshiyuki Ito, Junji Kitamichi, and Kenichi Kuroda. A MasterSlave Adaptive Load Distribution Processor Model on PCA. In IEEE, editor, Proc. of The 12th Reconfigurable Architectures Workshop, pages CD-ROM. IEEE, Apr. 2005.
	In this paper, we propose a new load distribution processor model that adapts hardware resources optimally and autonomously to target applications on dynamical reconfiguration devices. In the procedure of load distribution, the processor detects the load of task processing by itself and changes the kinds and number of resources optimally. We adopt the master-slave model, which consists of a management unit (master) for detecting an overload and distributing tasks and two or more processing units (slaves) for task processing. One of the features of this model is that it is possible to change the number of processing units without reconfiguring the management unit's structure. Moreover, in order to use this load distribution system efficiently, we propose a reordering unit that buffers data from processing units and outputs rearranged data. In this paper, we describe the requirements and organization of a management unit and processing units. Next, we implement the proposed model on real chips of PCA, a dynamical reconfiguration device, and measure the overheads of processing and reconfiguration. Finally, we evaluate the proposed model based on the experimental results. From the experiments, we show that our proposed model can reduce a designer's efforts to estimate the amount of hardware resources according to applications in advance.
[kuroken-02:2005]	Hiroaki Tanba, Yasuhiro Yamada, Junji Kitamichi, and Kenichi Kuroda. Hardware Implementations of High-Speed Network Monitors. In IEEE, editor, Proc. of 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test, pages 33-46. IEEE, Apr. 2005.
	Recently, many kinds of malicious attacks on the Internet such as Denial of Service (DoS) attacks are increasing, and many unnecessary packets waste network resources. Network monitors to watch and filtering these unnecessary packets have been proposed. However, in the present network monitors implemented using several servers and monitoring software, it will be difficult to watch in real time and remove unnecessary packets at the very high-speed backbone network such as intercontinental one. One of the methods to realize a real time network monitor is an implementation by the hardware. Therefore, in this research, we propose a hardware architecture that detects IP flooding and SYN Flood; these are kinds of DoS attacks. We design the hardware circuits in ASIC and FPGA. As the results of logic synthesis, we confirm that these detection circuits can work on the high-speed traffic such as more than 10 millions packets/sec.
[kuroken-03:2005]	Shuichi Watanabe, Junji Kitamichi, Kenichi Kuroda, and Youichi Takenaka. Proposal of Clustering Algorithm and Implementation using FPGA for Gene Expression Profile Analysis. In IEICE, editor, Proc. of 18th Circuits and Systems Workshop, pages 187-192. IEICE, Apr. 2005.
[kuroken-04:2005]	Kenji Asano, Junji Kitamichi, and Kenichi Kuroda. Proposal of a System Level Simulation Method for Dynamically Reconfigurable Architecture with Dynamic Generation and Elimination of Modules. In IPSJ, editor, Proc. of IPSJ DA Symposium 2005, pages 7-12. IPSJ, Aug. 2005.

Unrefereed Papers

[kitamiti-04:2005]	J. Nakajima, M. Honda, and J. Kitamichi. Implementation of Algorithm for Formal Verification of Real Time System using Real number Difference Logic. In In 26th PARTHENON Workshop, pages 19-26, May 2005.
	We propose new data structure and algorithms for a real number restricted arithmetic. In this real number restricted arithmetic, which consists of logical and real number variables and operators, we can describe specifications of real time systems. Proposed data structure is an extended BDD(Binary Decision Diagram), which is one of methods expressing Boolean functions. We also describe some algorithms for proposed data structure.
[kitamiti-05:2005]	M. Honda, J. Nakajima, and J. Kitamichi. Extended BDD Structure and Algorithm for Integer Difference Logic. In Summer LA Symposium, page 28, July 2005.
	We propose new data structure and algorithms for an integer restricted arithmetic. In this integer restricted arithmetic, which consists of logical and integer variables and operators, we can describe specifications of real time systems. Proposed data structure is an extended BDD(Binary Decision Diagram), which is one of methods expressing Boolean functions. We also describe some algorithms for proposed data structure.
[kitamiti-06:2005]	C. Saitou, J. Kitamichi, and K Kuroda. Proposal od Modeling Method of Realtime Systems using Extended SFL and Its Verification System. In In 27th PARTHENON Workshop, pages 45-52, Dec. 2005.
	The scale of systems implemented on a single chip has been increasing year by year and it has been becoming difficult to operate them properly with a single common clock. As a result, we cannot design the highly complicated systems using existing designing methods. Therefore, new designing methods are required to achieve complicated clocked systems including asynchronous systems. In this paper, we propose a method to extend SFL, one of the hardware description languages for synchronous sequential circuits, in order to describe mixed asynchronous and synchronous circuits or distributed systems. We also propose a method to describe the behaviors of real time systems with time constraints such as timeout. Moreover, we show a system modeling method and a system verification method using an example for the proposed language.
[kuroken-05:2005]	Tomoko OTSUKA, Keigo KURATA, Junji KITAMICHI, and Kenichi KURODA. Implementation of Simplified Back Propagation Algorithm On a Dynamically Reconfigurable Device PCA - 2. In IEICE, editor, IEICE Technical Report RECONF 2005-25, pages 73- 78. IEICE, June. 2005.
	We have been studying the implementation method of neural networks on Plastic Cell Architecture (JPCA), a fine-grained dynamically reconfigurable device, to execute neural networks processing effectively. Conventional PCA neuron models which we proposed for multi-layer neural networks, execute only static processing. In this paper, we propose implementation model of multi-layer neural networks with learning dynamically based on the back propagation algorithm. A proposed model can execute a learning process in parallel with a forward process. Connection information between neurons that each neuron must hold are reduced to simplify the learning process. Actually, we designed the proposed model on PCA-2, and simulated parallel processing of the learning process and the forward process. The proposed model uses dynamic routing functions of PCA with small routing area. Additionally, we discussed issues revealed by evaluation.
[kuroken-06:2005]	Keigo KURATA, Hiroyuki MORITA, Kazuya YOKOHARI, Yuichi OKUYAMA, Junji KITAMICHI, and Kenichi KURODA. Proposal of the Periodic Switching Method for Parallelism of State Renewed Neurons in the Hopfield Neural Networks. In PARTHENON Soc., editor, Proceedings of 26th PARTHENON Workshop 2005-5, pages 27-33. PARTHENON Soc., May 2005.
	The Hopfield neural networks are used for solving combinatorial optimization problems. In these networks, the state renewal methods of neurons are classified into synchronous type, sequential type, semi-synchronous type, nondeterministic type and so on. Using the synchronous type, the renewal speed is very fast but the convergence rate is very low. Conversely, the sequential type has a high convergence rate and a low speed. The semi-synchronous type has their middle performance, but to divide neurons into some groups properly is difficult because it depends on the applied problem. The convergence rate of the non-deterministic type is very high, but it needs many renewal steps and its hardware implementation is very hard. In this paper, we propose a new state renewal method of neurons to switch the synchronous type to the sequential type periodically. To apply for the N-queens problems, the four-coloring problems, and the maximum clique problems, we show the performance of the proposed method is high. In addition, our proposed method is applicable for wide ranged problems and very easy to implement on hardware.
[kuroken-07:2005]	Yasuhiro Sugita, Toshiyuki Ito, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Design and Implementation of a Processing Unit for Efficient Resource Utilization on PCA. In IEICE, editor, Proceedings of IEICE Society Conference (2005.09). IEICE, Sep. 2005.
[kuroken-08:2005]	Hironori Endo, Toshiyuki Ito, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Design of an LDPC Code Decoder with Variable Parameters on Dynamically Reconfigurable Devices. In PARTHENON Soc., editor, Proceedings of 27th PARTHENO Workshop 2005-12, pages 21-28. PARTHENON Soc., Dec. 2005.
	This paper describes design of a decoder on dynamically reconfigurable devices for LDPC codes, which has high transmission reliability even in low quality communication lines, and is suitable for hardware implementation due to its rather simple computation and easy parallelization. Optimum architecture, circuit complexity, and parallelism factor depend on transmission line quality, coderates, and decoding throughput. An LDPC code decoder with variable parameters is implemented on a dynamically reconfigurable device, Plastic Cell Architecture, and relation between decoding performance and average throughput is evaluated. It is suggested that by changing coderates dynamically, an average decoding throughput is improved with required decoding performance.
[kuroken-09:2005]	Yosuke Ikehata, Keigo Kurata, Yuichi Okuyama, Junji Kitamiti, and Kenichi Kuroda. Implementation of Scheduling Evaluation Environment for Dynamically Reconfigurable Device. In PARTHENON Soc., editor, Proceedings of 27th PARTHENO Workshop 2005-12, pages 29-36. PARTHENON Soc., Dec. 2005.
	Dynamically reconfigurable devices are attractive for their flexibility similar to that in software and their processability due to parallelism in hardware. They can implement various applications with time-sharing and scheduling by dividing their process. However, since scheduling itself depends on applications and their target devices, it must be evaluated on individual target devices and applications. In this paper, we propose a scheduling evaluation environment for dynamically reconfigurable devices. In this proposed environment, dynamically reconfigurable devices are virtually expressed by some parameters. They correspond to variable elements that depend on architectures or devices. Designers can evaluate scheduled results more easily by using this virtual environment rather than by using the actual devices. Although, we adapt this virtual device to Plastic Cell Architecture (PCA) in this paper, the evaluation environment can be applied to other dynamically reconfigurable devices.
[kuroken-10:2005]	Chizuru Saito, Junji Kitamichi, and Kenichi Kuroda. Proposal of Modeling Method of Realtime Systems using Extended SFL and its Verification System. In PARTHENON Soc., editor, Proceedings of 27th PARTHENO Workshop 2005-12, pages 45-52. PARTHENON Soc., Dec. 2005.
	The scale of systems implemented on a single chip has been increasing year by year and it has been becoming difficult to operate them properly with a single common clock. As a result, we cannot design the highly complicated systems using existing designing methods. Therefore, new designing methods are required to achieve complicated clocked systems including asynchronous systems. In this paper, we propose a method to extend SFL, one of the hardware description languages for synchronous sequential circuits, in order to describe mixed asynchronous and synchronous circuits or distributed systems. We also propose a method to describe the behaviors of real time systems with time constraints such as timeout. Moreover, we show a system modeling method and a system verification method using an example for the proposed language.
[okuyama-01:2005]	Keigo KURATA, Hiroyuki MORITA, Kazuya YOKOHARI, Yuichi OKUYAMA, Junji KITAMICHI, and Kenichi KURODA. Proposal of the Periodic Switching Method for Parallelism of State Renewed Neurons in the Hopfield Neural Networks. In PARTHENON Soc., editor, Proceedings of 26th PARTHENON Workshop 2005-5, pages 27-33. PARTHENON Soc., May 2005.
	The Hopfield neural networks are used for solving combinatorial optimization problems. In these networks, the state renewal methods of neurons are classified into synchronous type, sequential type, semi-synchronous type, nondeterministic type and so on. Using the synchronous type, the renewal speed is very fast but the convergence rate is very low. Conversely, the sequential type has a high convergence rate and a low speed. The semi-synchronous type has their middle performance, but to divide neurons into some groups properly is difficult because it depends on the applied problem. The convergence rate of the non-deterministic type is very high, but it needs many renewal steps and its hardware implementation is very hard. In this paper, we propose a new state renewal method of neurons to switch the synchronous type to the sequential type periodically. To apply for the N-queens problems, the four-coloring problems, and the maximum clique problems, we show the performance of the proposed method is high. In addition, our proposed method is applicable for wide ranged problems and very easy to implement on hardware.
[okuyama-02:2005]	Yasuhiro Sugita, Toshiyuki Ito, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Design and Implementation of a Processing Unit for Efficient Resource Utilization on PCA. In IEICE, editor, Proceedings of IEICE Society Conference (2005.09). IEICE, Sep. 2005.
[okuyama-03:2005]	Hironori Endo, Toshiyuki Ito, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Design of an LDPC Code Decoder with Variable Parameters on Dynamically Reconfigurable Devices. In PARTHENON Soc., editor, Proceedings of 27th PARTHENO Workshop 2005-12, pages 21-28. PARTHENON Soc., Dec. 2005.
	This paper describes design of a decoder on dynamically reconfigurable devices for LDPC codes, which has high transmission reliability even in low quality communication lines, and is suitable for hardware implementation due to its rather simple computation and easy parallelization. Optimum architecture, circuit complexity, and parallelism factor depend on transmission line quality, coderates, and decoding throughput. An LDPC code decoder with variable parameters is implemented on a dynamically reconfigurable device, Plastic Cell Architecture, and relation between decoding performance and average throughput is evaluated. It is suggested that by changing coderates dynamically, an average decoding throughput is improved with required decoding performance.
[okuyama-04:2005]	Yosuke Ikehata, Keigo Kurata, Yuichi Okuyama, Junji Kitamiti, and Kenichi Kuroda. Implementation of Scheduling Evaluation Environment for Dynamically Reconfigurable Device. In PARTHENON Soc., editor, Proceedings of 27th PARTHENO Workshop 2005-12, pages 29-36. PARTHENON Soc., Dec. 2005.
	Dynamically reconfigurable devices are attractive for their flexibility similar to that in software and their processability due to parallelism in hardware. They can implement various applications with time-sharing and scheduling by dividing their process. However, since scheduling itself depends on applications and their target devices, it must be evaluated on individual target devices and applications. In this paper, we propose a scheduling evaluation environment for dynamically reconfigurable devices. In this proposed environment, dynamically reconfigurable devices are virtually expressed by some parameters. They correspond to variable elements that depend on architectures or devices. Designers can evaluate scheduled results more easily by using this virtual environment rather than by using the actual devices. Although, we adapt this virtual device to Plastic Cell Architecture (PCA) in this paper, the evaluation environment can be applied to other dynamically reconfigurable devices.
[okuyama-05:2005]	Yuichi Okuyama Tsuyoshi Hamada, Naohito Nakasato. Prototyping and Evaluation of PCI Express Module for PGR System. In ., editor, IEICE Tech. report (RECONF2005-74), pages 13-18. IEICE, Dec. 2005.
	PGR(Processor Generator for Reconfigurable systems) is a software for developing FPGA-based computing engine(FBCE) specialized for particle-balsed simulations. In the PGR system, components which depends on individual hardware platforms are hidden under the hardware abstraction layer: HAL. PGR can support multiple hardware platform by converting the HAL modules for the PROGRAPE-3 system and the Cray-XD1 system. In this paper, we have implemented new HAL module for the XPDKSXGX40 system which is commercially available from PLD Applications, Inc. The PXPDKSXGX40 system is one of the earlies FBCE system that is implemented PCI-Express interface. This paper is novel report that an FBCE using PCI-Express interface can be implemented a practical application.

Academic Activities

[kitamiti-07:2005]	Kitamichi J., 2005. Member, IEEE
[kitamiti-08:2005]	Kitamichi J., 2005. Member, IPSJ
[kitamiti-09:2005]	Kitamichi J., 2005. Member, IEICE
[kuroken-11:2005]	Kenichi Kuroda, 2005. Member of Management Board, PARTHENON Society (NPO)
[kuroken-12:2005]	Kenichi Kuroda, 2005. Member of Student Activity Support Committee, IEICE
[okuyama-06:2005]	Yuichi Okuyama, 2005. IEICE Regular member
[okuyama-07:2005]	Yuichi Okuyama, 2005. IPSJ Regular member

Patents

[okuyama-08:2005]

S. Sedukhin, T. Miyazaki, K. Kuroda, H. Ohi, and Y. Okuyama. Computing Process Unit Applied PAT.NO.2006-074097 Japan, March 2005.

Ph.D and Other Theses

[kitamiti-10:2005]	Noriaki Kaida. Graduation Thesis: Proposal of Hardware Design Method using UML and VerilogHDL, University of Aizu, 2005. Thesis Advisor: Kitamichi, J.
[kitamiti-11:2005]	Jun Muraoka. Graduation Thesis: Verification of Control Units in Pipeline Processor with a CTL Model Checking Tool: VIS, University of Aizu, 2005. Thesis Advisor: Kitamichi, J.
[kitamiti-12:2005]	Hajime Katayama. Graduation Thesis:Study on FPGA Implementation of 16-QAM Demodulator, University of Aizu, 2005. Thesis Advisor: Kitamichi, J.
[kitamiti-13:2005]	Takayoshi Muromoto. Graduation Thesis: FPGA Implementation of Motion Estimation for H.264/AVC, University of Aizu, 2005. Thesis Advisor: Kitamichi, J.
[kuroken-13:2005]	Yoshuke Ikehata. Master Thesis: Study on Scheduler Evaluation Environment Considering Autonomous Reconfigurable Applications on PCA, University of Aizu, 2005. Thesis Advisor: Yuichi Okuyama.
[kuroken-14:2005]	Hironori Endo. Master Thesis: Design of an LDPC Decoder with Variable Parameters on a Dynamically Reconfugrable Device, University of Aizu, 2005. Thesis Advisor: Yuichi Okuyama.
[kuroken-15:2005]	Tomoki Kamiyama. Master Thesis: Proposal of a Design Method for Self-reproductive Applications on Plastic Cell Architecture, University of Aizu, 2005. Thesis Advisor: Yuichi Okuyama.
[kuroken-16:2005]	Kenji Asano. Master Thesis: Research on System Level Simulation for Dynamically Reconfugurable Architecture, University of Aizu, 2005. Thesis Advisor: Junji Kitamichi.
[kuroken-17:2005]	Sou Inoue. Master Thesis: Research on Hardware Realization of Needleman-Wunsch Algorithm for Genome Homology Analysis, University of Aizu, 2005. Thesis Advisor: Junji Kitamichi.
[kuroken-18:2005]	Junichi Nakajima. Master Thesis: Research on Modeling Method of Pipeline Processors using UML and SystemC, University of Aizu, 2005. Thesis Advisor: Junji Kitamichi.
[kuroken-19:2005]	Chizuru Saito. Master Thesis: Study on a Modeing Language and a Simulation Environment for Asynchronous Distributed Systems, University of Aizu, 2005. Thesis Advisor: Junji Kitamichi.
[kuroken-20:2005]	Hiroaki Tanba. Master Thesis: Study on Automatic Test Pattern Generation for Asynchronous Distributed Systems, University of Aizu, 2005. Thesis Advisor: Junji Kitamichi.

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