Operating Systems Laboratory

Stanislav Sedukhin Professor	Minyi Guo Associate Professor	Hitoshi Oi Assistant Professor	Wang Hui Visiting Researcher
Baoliu Ye Visiting Researcher

Parallel fused computer architecture and algorithms Computationally Efficient Parallel Matrix-Matrix Multiplication on the Torus Parallel Blocked Algorithm for the Algebraic Path Problem New Models of Grid and Ubiquitous Computing for Image Processing Power-Aware Instruction Scheduling for Embedded Systems Cooperative Cache Based Streaming Schedule Scheme for On-demand Media Services on Overlay Networks Workload Analysis of High-Performance Computing Servers Hardware Java Virtual Machine for Embedded Processors Low Power Design of Wireless Sensor Network Node Parallel fused computer architecture and algorithms In the forthcoming Billion transistor era, it is necessary to find new technology-scalable processor architecture to use this huge transistor budget efficiently and meet both the physical/technological limitations (wire delays, power consumption, memory wall, increasing logic/pin ratio, etc.) and the requirements of future applications.To address the semiconductor scaling challenges of high-performance processors, particularly in instruction selection, execution, and bypass, the project evaluates a new class of processor organization to resolve the existing semiconductor constrains. The project has two major research goals: Research of high-performance technology-scalable computer architecture; Porting and performance evaluation of the basic linear algebra, DSP, networking, and multimedia kernels on proposed architecture. Our theoretical and experimental results indicate that proposed fused computer architecture can be very useful for fast solution of many matrix-formulated problems. New Models of Grid and Ubiquitous Computing for Image Processing The main purpose of this research is to explore new software models/toolkits, named Ubiquitous Multi-Processor (UMP) system, to support distributed application development over the emerging ubiquitous/pervasive computing environment, such as ubiquitous computing, Peer-to-Peer (P2P) computing, and mobile computing environments. In the proposed application scenario, there are many PCs equipped with some UMPs. These PCs are distributed over different domains (each PC belongs and only belongs to one domain). There also has a resource router in each domain taking charge of UMP management request processing. In the system, the behaviors of UMPs are controlled by corresponding resource router. Once it registers to the resource router successfully, a UMP will listen and accept for the task scheduled by the resource router. the UMP will also update it status information to the resource router when a task is finished. To support mobile computing environments, the resource router should be aware of the location of mobile users and be able to locate available UMPs from the nearest domain, so as to reduce the communication cost for the request. Power-Aware Instruction Scheduling for embedded systems In most of compilers, the goal of traditional instruction scheduling algorithms is to improve performance in terms of execution time. This can be done by some wellknown ways such as superblock scheduling, hyperblock scheduling, and treegion scheduling. These scheduling strategies focus mainly on increasing performance through increasing the amount of instruction-level parallelism in program code. However, in VLIW (very long instruction word) architectures, an instruction word consists of a variable number of individual instructions. Therefore the step power and peak power consumption vary significantly depending on the parallel schedule generated by compiler. Power variation reduction without losing execution speed is an important scheduling constraint for embedded VLIW architectures. In this research, we studied some power-aware scheduling strategies for VLIW processors. These scheduling methods include low power scheduling for basic blocks with integer programming Modulo and Software Pipelining for loops Register allocation and cache reuse for power reduction. Cooperative Cache Based Streaming Schedule Scheme for On-demand Media Services on Overlay Networks Recently, we have witnessed a tremendous growth of interests in streaming continuous media such as video data over the Internet. However, how to provide true on-demand streaming services with VCR functionality is still a challenging task, especially when their scalability is required. In this paper, we proposed CoopStream, a novel streaming scheme, to address this challenge in the context of overlay networks. At the client side, we proposed to use a dualchannel cache management mechanism to dynamically adjust the cache contents based on its current playing state, so as to support VCR operations locally. On the server side, we exploit the temporal relationship among asynchronous streaming requests to schedule streams. This enables us to reduce significantly the server load by redirecting streaming requests to the clients that can serve those requests. Simulation results show that, CoopStream is capable of providing continuous streaming services that are scalable in terms of the server bandwidth consumed. Workload Analysis of High-Performance Computing Servers To design a power and cost-efficient high-performance server, it is important to understand the behavior of applications and their effect on the hardware components. We have chosen database servers, which is one of most commonly executed workloads on high-performance systems, and have been investigating their characteristics. In particular, currently at the Operating Systems Laboratory, we are working on the Open Source Development Labs' Database Test suites (OSDL DBT), which are open source implementations of TPC benchmark programs. Possible outcomes from this project include development of analytical models of server systems, server simulation programs with graphical user interface that can be used for classroom teaching for the computer systems course, and optimizations of hardware and software components (such as memory hierarchy, disk systems) for performance improvement. For this purpose, we have set up an experimental server system with Linux and Windows operating systems running on Intel and AMD processors, and installed a various tools and benchmark programs including OSDL dbt2 (mentioned above), oprofile and VMware server. Hardware Java Virtual Machine for Embedded Processors The program execution on the modern portable devices have a different style from the traditional systems: programs are downloaded over the network and executed on the various hardware configurations including processor types, memory size and hierarchy, display devices and resolutions. This variation of the platform configuration necessitates the application to be written in a platform-independent way, and its most popular solution is the virtual machine: an abstract microprocessor architecture and its instruction set. The platform-independent feature of the virtual machine comes with a performance penalty: the processor of the portable device needs to run an interpretor to convert the virtual machine instructions to its native instructions. This interpretation is an overhead to the application's workload. A remedy for this issue which is commonly adopted on the desktop and server platforms is called the just-in-time compilation (JIT), which compiles frequently executed functions (methods) into native instructions. However, compilation overhead (execution time and power consumption) and expanded program sizes are disadvantages of JIT to be used for the portable devices. One promising solution for this problem is to translate the virtual machine instructions into native instruction by hardware. In this type of processors, a small translation module is inserted between the instruction fetch and decode stages of the pipeline. When a simple virtual machine instruction is fetched, the translation module generates a sequence of corresponding native instructions which are fed to the decode stage. When a complex virtual machine instruction is fetched, the translation module issues a (native) branch instruction whose target is at the starting address of the subroutine that emulates the complex virtual machine instruction. In principle, the modifications to the base microprocessor are localized to the translation module and therefore minimum. So far, we have investigated the behavior of the Java applications that are likely to be executed on embedded processors. We proposed two techniques to further improved the performance of the hardware-translation based JVM and published two papers in this topic. The topics of further investigations include the development of execution environment for both Java bytecodes and native codes, evaluation of power consumption reduction by the hardware-translation, and a simulator program with graphical user interface that explains how a single processor core can execute multiple instruction sets using the hardware-translation (which should be used for educational purpose). We became an academic member of the Embedded Microprocessor Benchmark Consortium (EEMBC) and obtained their GrinderBench (Java benchmark programs for embedded processors). Low Power Design of Wireless Sensor Network Node Wireless sensor networks consist of a large number of nodes that are distributed over large geographical regions. Each node is made of a microcontroller, memory, radio communication devices, a battery and various sensors (such as temperature or light). Neighbor nodes autonomously communicates each other and form a network to collect and aggregate necessary data. It is likely to deploy many nodes to form a sufficient size of network. Therefore, each node must be inexpensive. Also, once deployed, it is difficult (if not impossible) to repair a malfunctioning node or to replace batteries. While there are many issues caused by these physical constraints on the sensor node, we are in particular interested in how to write programs for the sensor network in a concise way for two reasons. First, the size of program memory is limited on the node and simply a large program cannot be fitted. Second, the program of the node needs to be modified or completely replaced from time to time. Often, the only method to reprogram the sensor nodes is by the wireless connection. However, to receive program packets over the wireless network connection consumes a significant amount of battery power. Consequently, a concisely written program leads to a shorter radio communication time and results in lower power consumption. One possible approach to write programs for sensor network nodes concisely is to use a virtual machine (Mat'e). In this approach, the program is represented by the instructions of the virtual machine which are much denser than the native instructions of the microcontroller on the node. However, while the program size can be much smaller than the native instructions, the execution of programs in virtual instructions can be costly due to the interpretation of (dense) virtual instructions. Therefore, it has been pointed out that this approach is feasible when the node is frequently reprogrammed but the program is infrequently executed. We and the research group led by Dr. Chris Bleakley, Lecturer in the School of Computer Science and Informatics at University College Dublin, Ireland, started working on the design of low power virtual machine for sensor network nodes. We will take two approaches. First, we analyze the representative applications on the sensor networks and redesign the instruction set for the virtual machine. Second, we identify the instructions that are costly to be executed by the interpretation and implement them by the hardware. We held a kick-off meeting at UCD in May and will start working from June. We aim to design the virtual instruction set, develop HDL models to implement the virtual machine using the system-on-chip (SoC) technique, and evaluate their performance and power consumption.

Refereed Journal Papers

[minyi-01:2005]	Baoliu Ye, Minyi Guo, Jingyang Zhou, and Daoxu Chen. A Multicast Based ASnonymous Information Sharing Protocol for Peer-toPeer Systems. IEICE Transactions on Information and Systems, E89- D(2):581-588, 2006.
	A fundamental problem in a pure P2P file sharing system is how to protect the anonymity of peer nodes when providing efficient datga access services. Most of existing work mainly focus on how to provide the initator anonymity, but neglect the anonymity of the responder. In this paper, we propose a multicastbased protocol, called Mapper, for efficient file sharing with mutual anonymity. Mapper replicates requested files inside the multicast group, so that the file distribution can be adjusted adaptively and the cost for multcast can be further reduced.
[minyi-02:2005]	Hui Wang, Minyi Guo, and Daming Wei. Message Scheduling for Irregulart Data Redistribution in Parallelizing Compilers. IEICE Transactions on Information and Systems, E89-D(2):418-424, 2006.
	In parallelizing compilers on distributed memory systems, distributions of irregular sized array blocks are provided for load balancing and irregular problems. The irregular data redistribution is different from the regular block-cyclic redistribution. This paper is devoted to scheduling message for irregular data redistribution. that attempt to obtgain suboptimal solutions while satisfying the minimal communication costs condition and minimal step condition.
[minyi-03:2005]	Weng-Long Chang and Minyi Guo Michael Ho. Fast Parallel Molecular Algorithms for DNA-based Computation: Factoring Integers. IEEE Transactions on Nanobioscience, 4(2):149-163, 2005.
	The RSA public-key cryptosystem is an algorithm that converts input data to an unrecognizable encryption and converts the unrecognizable data back into its original decryption form. The security of the RSA public-key cryptosystem is based on the difficulty of factoring the product of two large prime numbers. This paper demonstrates to factor the product of two large prime numbers, and is a breakthrough in basic biological operations using a molecular computer. In order to achieve this, we propose three DNA-based algorithms for parallel subtractor, parallel comparator, and parallel modular arithmetic that formally verify our designed molecular solutions for factoring the product of two large prime numbers. Furthermore, this work indicates that the cryptosystems using public-key are perhaps insecure and also presents clear evidence of the ability of molecular computing to perform complicated mathematical operations.
[minyi-04:2005]	Minyi Guo and Yi Pan. Improving communication scheduling for array redistribution. Journal of Parallel and Distributed Computing, 65(5):553-563, 2005.
	Many scientific applications require array redistribution when the programs run on distributed memory parallel computers. It is essential to use efficient algorithms for redistribution, otherwise the performance of the programs will degrade considerably. The redistribution overheads consist of two parts: index computation and inter-processor communication. If there is no communication scheduling in a redistribution routine, the inter-processor communication will incur a larger communication idle time when there exists node contention and/or difference among message lengths during one particular communication step. In order to solve this problem, in this paper, we propose an efficient scheduling scheme that not only minimizes the number of communication steps and eliminates node contention, but also minimizes the difference of message lengths in each communication step. Thus, the communication idle time is reduced in redistribution routines.
[minyi-05:2005]	Minyi Guo, Weng-Long Chang, and Jiannong Cao. Using Sticker to Solve the 3-Dimensional Matching Problem in Molecular Supercomputers. International Journal of High Performation Computing and Networking, 1(3):128-139, 2005.
	Aldeman demonstrated that DNA (Deoxyribonucleic acid) strands could be applied for dealing with solutions to an instance of the NP-complete Hamiltonian path problem (HPP) (Adleman, 1994). The Adleman techniques could also be used to solve the NP-complete satisfiability (SAT) problem (the first NP-complete problem) (Lipton, 1995). Furthermore, sticker is used for enhancing the Adleman-Lipton model (Roweis et al., 1999). In this paper, we first use sticker to construct solution space of DNA library sequences for the 3-dimensional matching problem. Then, in the Adleman-Lipton model, we propose an algorithm to remove illegal solution and find legal solution for the 3-dimensional matching problem from solution space of sticker. Finally, a simulation result for our algorithm is generated.
[minyi-06:2005]	Minyi Guo and Weng-Long Chang. Solving the Independent-set Problem in a DNA-based Supercomputer Model. Parallel Processing Letters, 15(4):469-479, 2005.
[sedukhin-01:2005]	M. Soliman and S. Sedukhin. Performance Evaluation of the BLAS on the Trident Processor. Parallel Processing Letters, 15(4):407- 414, 2005.
	Different subtasks of an application usually have different computational, memory, and I/O requirements that result in different needs for computer capabilities. Thus, the more appropriate approach for both high performance and simple programming model is designing a processor having multi-level instruction set architecture (ISA). This leads to high performance and minimum executable code size. Since the fundamental data structures for a wide variety of existing applications are scalar, vector, and matrix, our research Trident processor has three-level ISA executed on zero-, one-, and two-dimensional arrays of data. These levels are used to express a great amount of fine-grain data parallelism to a processor instead of the dynamical extraction by a complicated logic or statically with compilers. This reduces the design complexity and provides high-level programming interface to hardware. In this paper, the performance of Trident processor is evaluated on BLAS, which represent the kernel operations of many data parallel applications. We show that Trident processor proportionally reduces the number of clock cycles per floating-point operation by increasing the number of execution datapaths.

Referred Proceeding Papers

[hitoshi-01:2005]	Hitoshi Oi. On the Design of the Local Variable Cache in a Hardware Translation-Based Java Virtual Machine. In Proceedings of ACM SIGPLAN/SIGBED 2005 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), pages 87-94. ACM SIGPLAN/SIGBED, 2005.
	Hardware bytecode translation is a technique to improve the performance of the Java Virtual Machine (JVM), especially on the portable devices for which dynamic compilation is infeasible. However, since the translation is done on a single bytecode basis, it is likely to generate frequent memory accesses for local variables which can be a performance bottleneck. In this paper, we propose to add a small register file to the datapath of the hardwaretranslation based JVM and use it as a local variable cache. We evaluate the effectiveness of the local variable cache against the size of the local variable cache which determines the chip area overhead and the operating speed. We also discuss the mechanisms for the efficient parameter passing and the onthe-fly profiling With two types of exceptions, a 16-entry local variable cache achieved hit ratios of 60 to 98%. The first type of exceptions is represented by the FFT, which accesses more than 16 local variables. In this case, on-thefly profiling was effective. The hit ratio of 16-entry cache for the FFT was increased from 44 to 83%. The second type of exception is represented by the SAXON XSLT processor for which cold misses were significant. The proposed parameter passing mechanism turned 6.4 to 13.3% of total accesses from miss to hit to the local variable cache.
[minyi-07:2005]	Baoliu Ye, Minyi Guo, and Daoxu Chen. An IP Routing Inspired Information Search Scheme for Semantic Overlay Networks. In Proceedings of 2005 International Conference on High Performance Computing and Networks (HPCC 2005), Sorrento, Italy, September 2005. Springer.
	Lecture Notes in Computer Science
[minyi-08:2005]	Yoshihiro Saitoh, Kenichi Sumitomo, Takato Izaiku, Takamasa Oono, Kazuhiko Yagyu, Hui Wang, and Minyi Guo. JXTPIA: A JXTABased P2P Network Interface and Architecture for Grid Computing. In Proceedings of 2005 International Conference on High Performance Computing and Networks (HPCC 2005), Sorrento, Italy, September 2005. Springer.
	Lecture Notes in Computer Science
[minyi-09:2005]	Jingling Xue, Qingguang Huang, and Minyi Guo. Enabling Loop Fusion and Tiling for Cache Performance by Fixing Fusion-Preventing Data Dependences. In Proceedings of the 2005 International Conference on Parallel Processing (ICPP 2005), Oslo, Norway, June 2005. University of Oslo, IEEE CS Press.
[minyi-10:2005]	Guojun Wang, Yingjun Lin, and Minyi Guo. A Scalable and Reliable Multiple Home Regions Based Location Service in Mobile Ad Hoc Networks. In Proceedings of the 2005 International Conference on Embedded and Ubiquitous Computing (EUC 2005), Nagasaki, Japan, December 2005. IFIP, Springer.
	Lecture Notes in Computer Science 3824
[minyi-11:2005]	Jiannong Cao, Yinghao Li, and Minyi Guo. Process Migration for MPI Applications based on Coordinated Checkpoint. In Proceedings of the 11th International Conference on Parallel and Distributed Systems (ICPADS 2005), Fukuoka, Japan, July 2005. IEEE, IEEE CS Press.
[minyi-12:2005]	Baoliu Ye, Minyi Guo, Daoxu Chen, and Sanglu Lu. A Heuristic Routing Algorithm for Degree-Constrained Minimum Overall Latency Application Layer Multicast. In Proceedings of the 2005 International Symposium on Parallel and Distributed Processing and Applications (ISPA 2005), Nanjing, China, November 2005. IEEE, Nanjing University, Springer.
	Lecture Notes in Computer Science 3758
[minyi-13:2005]	Weng-Long Chang, Minyi Guo, Michael (Shan-Hui) Ho, and SienTang Tsai. Communication-Free Data Alignment for Arrays with Exponential References Using Elementary Linear Algebra. In Proceedings of the 2005 International Symposium on Parallel and Distributed Processing and Applications (ISPA 2005), Nanjing, China, November 2005. IEEE, Nanjing University, Springer.
	Lecture Notes in Computer Science 3758
[minyi-14:2005]	Kenichi Sumitomo, Takato Izaiku, Yoshihiro Saitoh, Hui Wang, Minyi Guo, and Jie Huang. Effective Resource Allocation in a JXTABased Grid Computing Platform JXTPIA. In Proceedings of the 2005 International Symposium on Parallel and Distributed Processing and Applications (ISPA 2005), Nanjing, China, November 2005. IEEE, Nanjing University, Springer.
	Lecture Notes in Computer Science 3758
[sedukhin-02:2005]	S. Sedukhin and M. Soliman. A Matrix Processor for Mathintensive Applications. In Editor S. Dascalu, editor, Proceedings of the ISCA 18th International Conference on Computer Applications in Industry and Engineering (CAINE 2005), pages 109-114, Honolulu, Hawaii, Nov. 2005. ISCA, ISCA.
	Trident is a research processor, which consists of a set of parallel lanes combined with a fast scalar core. Like vector architectures, each Trident lane contains a set of vector pipelines and a slice of register file. In addition to scalar registers, Trident has two types of registers to store and cyclically shift 1-D array of data within and across the parallel lanes. One key point of our architecture is the local communication within and across lanes to overcome the limitations of the future VLSI technology. Another key point is the effective processing of a mixture of 0-D (scalar), 1-D (vector), and 2-D (matrix) arrays of data, which are the fundamental data structures for many math-intensive data parallel applications. Moreover, the architecture of the Trident processor is scalable and its scalability does not require more fetch, decode, or issue bandwidth, but requires replicating the number of lanes. This paper describes the main features of the Trident processor and demonstrates its performance on the QR factorization algorithm.
[sedukhin-03:2005]	A. Takahashi and S. Sedukhin. Parallel Blocked Algorithm for Solving the Algebraic Path Problem on a Matrix Processor. In Editor L.T. Yang, editor, Lecture Notes in Computer Science, vol. 3726: Proc. of the First International Symposium on High Performance Computing and Communications (HPCC 2005), pages 786-795, Sorrento, Italy, Sept. 2005. University of Naples, Springer.
	This paper presents a parallel blocked algorithm for the algebraic path problem (APP). It is known that the complexity of the APP is the same as that of the classical matrix-matrix multiplication; however, solving the APP takes much more running time because of its unique data dependencies that limits data reuse drastically. We examine a parallel implementation of a blocked algorithm for the APP on the onechip Intrinsity FastMATH adaptive processor, which consists of a scalar MIPS processor extended with a SIMD matrix coprocessor. The matrix coprocessor supports native matrix instructions on an array of 4x4 processing elements. Implementing with matrix instructions requires us to transform algorithms in terms of matrix-matrix operations. Conventional vectorization for SIMD vector processing deals with only the innermost loop; however, on the FastMATH processor, we need to vectorize two or three nested loops in order to convert the loops to equivalent one matrix operation. Our experimental results show a peak performance of 9.27 GOPS and high usage rates of matrix instructions for solving the APP. Findings from our experimental results indicate that the SIMD matrix extension to (super)scalar processor would be very useful for fast solution of many matrix-formulated problems.
[sedukhin-04:2005]	A. Zekri and S. Sedukhin. Computationally Efficient Parallel Matrix-Matrix Multiplication on the Torus. In Editor K. Joe, editor, Proc. of the 6th International Symposium on High-Performance Computing (ISHPC-VI), pages 125-131, Nara, Japan, Sept. 2005. IPSJ, Nara Women's University.
	In this paper, we represent the computation space of the (nxn)-matrix multiplication problem as a 3-D torus. All possible time-minimal scheduling vectors needed to activate the computations inside the corresponding 3-D index points at each step of computation are determined. Using the well-known projection method to allocate the scheduled computations to the processing elements, the resulting array processor that minimizes the computation time is a 2-D torus with nxn processing elements. For each optimal time scheduling function, three optimal array allocations are obtained from projection. All the resulting allocations of all the optimal scheduling vectors can be classified into three groups. In one group, matrix C is stationary and both matrices A and B are moving between neighbor processors. The well-known Cannon CT algorithm belongs to this group. In another group, matrix A is fixed and both matrices B and C are shifted. In the third group, matrix B is fixed while both matrices A and C are shifted. The obtained array processor allocations need n computation steps to multiply nxn dense matrices.
[sedukhin-05:2005]	M. Soliman, S. Mohammed, S. Hassan, and S. Sedukhin. A Highly Efficient Implementation of Back Propagation Algorithm by Matrix ISA. In Editor Osano, M., editor, Proc. of the 8th International Conference on Human and Computers (HC-2005), pages 312- 319, Aizu-Wakamatsu, Japan, Aug. - Sept. 2005. The University of Aizu, The University of Aizu.
	Back Propagation (BP) training algorithm has received intensive research efforts to exploit its parallelism in order to reduce the training time for complex problems. One direction of such efforts focused on Matrix Back Propagation (MBP) implementation of BP on a specific parallel or scalar processor type. This paper discusses the implementation of MBP using scalar, vector, and matrix ISA. Besides, it shows that the performance of the MBP is improved by switching form scalar to vector ISA and form vector to matrix ISA. On a practical application, speech recognition, the speedup of training a neural network using unrolling scalar over scalar ISA is 1.83. On 8 parallel lanes, the speedup of using vector, unrolling vector, and matrix ISA are respectively 10.3, 11.85, and 15.38, where the maximum theoretical speedup is 16. Our results show that the use of matrix ISA gives a performance close to the optimal because of reusing the loaded data, decreasing the loop overhead, and overlapping the memory operations by arithmetic operations.

Books

[minyi-15:2005]	Yi Pan, Daoxu Chen, Minyi Guo, Jiannong Cao, and Jack Dongarra. Parallel and Distributed Computing with Applications. Number 3758 in Lecture Notes in Computer Science. Springer-Verlag, Berlin, 2005.
[minyi-16:2005]	Guihai Chen, Yi Pan, Minyi Guo, and Jian Lu. Workshop of Parallel and Distributed Computing with Applications. Number 3759 in Lecture Notes in Computer Science. Springer-Verlag, Berlin, 2005.
[minyi-17:2005]	Laurence Tianruo Yang, Makoto Amamiya, Zhen Liu, Minyi Guo, and Franz J. Rammig. Embedded Software and Systems, First International Conference. Number 3824 in Lecture Notes in Computer Science. Springer-Verlag, Berlin, 2005.
[minyi-18:2005]	Zhaohui Wu, Chun Chen, Minyi Guo, and Jiajun Bu. Embedded and Ubiquitous Computing. Number 3605 in Lecture Notes in Computer Science. Springer-Verlag, Berlin, 2005.
[minyi-19:2005]	Laurence Tianruo Yang and Minyi Guo. High Performance Computing: Paradigm and Infrastructure. John Wiley & Sons, Boston, 2005.
[minyi-20:2005]	Minyi Guo and Laurence Tianruo Yang. New Horizons of Parallel and Distributed Computing. Springer, New York, 2005.

Grants

[hitoshi-02:2005]	Hitoshi Oi. The University of Aizu Competitive Research Fund, 2005-2006.
[minyi-21:2005]	Minyi Guo. Tecommunication Advancement Foundation, 2004-2005.
[minyi-22:2005]	Minyi Guo. Japan Science and Technology Agency, 2005.

Academic Activities

[hitoshi-03:2005]	Hitoshi Oi, Feb. 2006. Professional Member, IEEE/CS
[hitoshi-04:2005]	Hitoshi Oi, Apr. 2005. Professional Member, ACM
[hitoshi-05:2005]	Hitoshi Oi, Jan. 2006. Academic Member, representative for Aizu University, EEMBC
[hitoshi-06:2005]	Hitoshi Oi, Jul. 2005. Reviewer for The Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'05)
[hitoshi-07:2005]	Hitoshi Oi, Oct. 2005. Reviewer for Microprocessors and Microsystems, Elsevier
[hitoshi-08:2005]	Hitoshi Oi, Oct. 2005. Review for the International Journal of Computers and Applications ACTA Press
[hitoshi-09:2005]	Hitoshi Oi, Nov. 2005. Reviewer for IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)
[minyi-23:2005]	Minyi Guo, 2002-. IEICE member
[minyi-24:2005]	Minyi Guo, 2000-. IEEE, IEEE Computer Society member
[minyi-25:2005]	Minyi Guo, 2000-. ACM member
[minyi-26:2005]	Minyi Guo, 1995-. IPSJ member
[minyi-27:2005]	Minyi Guo, December 2005. Steering Committee Chair, The 2005 International Symposium on Parallel and Distributed Computing with Applications (ISPA2005).
[minyi-28:2005]	Minyi Guo, August 2005. Steering Committee Chair, the 2005 International Conference on Embedded and Ubiquitous Computing
[sedukhin-06:2005]	S Sedukhin, Apr. 2005. IEEE CS, member
[sedukhin-07:2005]	S Sedukhin, Apr. 2005. ACM, member
[sedukhin-08:2005]	S Sedukhin, Apr. 2005. IEICE, member
[sedukhin-09:2005]	S Sedukhin, Apr. 2005. IASTED Technical Committee on Parallel Processing, member
[sedukhin-10:2005]	S Sedukhin, Apr. 2005. International Journal of Neural, Parallel & Scientific Computations, Member of the Editorial Board
[sedukhin-11:2005]	S Sedukhin, Apr. 2005. International Journal of Parallel Processing Letters, Member of the Editorial Board
[sedukhin-12:2005]	S Sedukhin, Sept. 2005. The 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC005), Singapore, Stearing Committee Member
[sedukhin-13:2005]	S Sedukhin, Dec. 2005. The International Conference on Parallel and Distributed Computing, Applications, and Technologies (PDCAT 2005), Program Committee Member
[sedukhin-14:2005]	S Sedukhin, Feb. 2006. International Conference on Parallel and Distributed Computing and Networks, Program Committee Member

Patents

[sedukhin-15:2005]

S. Sedukhin, K. Kuroda, T. Miyazaki, Y. Okuyama, and H. Oi. Cellular Array Processor, P060012, No. 50600506507, 2006.3.17 (pending), March 2006.

Ph.D. and Other Theses

[minyi-29:2005]	Kazuhiko Yagyu. Master Thesis: Implemenation of a Message Passing Communication Interface in a JXTA-based Grid Computing Platform JXTPIA, University of Aizu, 2005. Thesis Advisor: Minyi Guo.
[minyi-30:2005]	Bin-Gang Deng. Master Thesis: Unit Decompsition of Pipelined Parallelism using Genetic Algorithms and Integer Linear Programming, University of Aizu, 2005. Thesis Advisor: Minyi Guo.
[minyi-31:2005]	Yuusuke Endou. Graduation Thesis: The Implementation of a Java Based Task Migration Software, University of Aizu, 2005. Thesis Advisor: Minyi Guo.
[minyi-32:2005]	Ryo Amano. Graduation Thesis: Consideration of Data Transmission System Using JNI, University of Aizu, 2005. Thesis Advisor: Minyi Guo.
[minyi-33:2005]	Kouki Ookoshi. Graduation Thesis: JXTPIA P2P Network Monitoring and Peer Performance Evaluation, University of Aizu, 2005. Thesis Advisor: Minyi Guo.
[sedukhin-16:2005]	Akihito Takahashi. Master Thesis: Matrix Computations for Path Problems, University of Aizu, 2006. Thesis Advisor: Sedukhin, S.
[sedukhin-17:2005]	Ryosuke Kato. Master Thesis: Efficiency of Network Operations using Hyper Threading Technology with SMP, University of Aizu, 2006. Thesis Advisor: Sedukhin, S.
[sedukhin-18:2005]	Norihiko Murase. Graduation Thesis: Detecting Matrix Operations from a Sequential Program, University of Aizu, 2006. Thesis Advisor: Sedukhin, S.
[sedukhin-19:2005]	Kazuya Uehira. Graduation Thesis: Development of the Educational System for Embedded Operating Systems, University of Aizu, 2006. Thesis Advisor: Sedukhin, S.
[sedukhin-20:2005]	Shinichi Aoki. Graduation Thesis: Simulation of Trident Processor, University of Aizu, 2006. Thesis Advisor: Sedukhin, S.

Others

[minyi-34:2005]	Minyi Guo. Editor in Chief, International Journal of Embedded Systems
[minyi-35:2005]	Minyi Guo. Editor, Journal of Embedded Computing
[minyi-36:2005]	Minyi Guo. Editor, International Journal of Web and Grid Services
[minyi-37:2005]	Minyi Guo. Editor, International Journal of High Performance Computing and Networking
[minyi-38:2005]	Minyi Guo. Editor, International Journal of Computer and Applications
[minyi-39:2005]	Minyi Guo. Editor, Journal of Pervasive Computing and Communications
[minyi-40:2005]	Minyi Guo. Guest Editor, Special issue on Parallel and Distributed Computing and Networking, IEICE Transactions on Information and Systems

2007 THE UNIVERSITY OF AIZU ALL RIGHTS RESERVED