Computer Education Laboratory

Kenichi Kuroda Professor	Junji Kitamichi Associate Professor	Yuichi Okuyama Assistant Professor

The academic area of the laboratory mainly covers computer design methodology. Educational course design for VLSI design, formal verification and reconfigurable computing are the major themes of this lab. Education: We have been developing an education program of VLSI design based on VDEC (VLSI Design and Education Center) support. VDEC offers various kinds of design tools without license costs and accepts chip fabrication orders in low price. This program was started as a joint research with Prof. Shima, who left from this university in 2004, in Computer Architecture Laboratory in 2001. Web-based manuals for HDL design, verification, and layout tools have been developed and are being updated depending on VDEC support tools every year. This year, as same as in 2005, we have been collaborating with Prof. Miyazaki who joined this university from April, 2005 at Computer Organization Lab. In 2006, members of our laboratory are three professors, 1 doctoral program students, 10 master program students, and 12 graduate thesis students. Among the above students, 7 entered the graduate school of our university and 11 students got jobs after graduation. Research: We have been proceeding the joint research with NTT Network Innovation Laboratories on Library Modules Development for Dynamically Reconfigurable Devices, PCA (Plastic Cell Architecture) since 2003. Among these joint research years, we developed various kinds of library modules in order to construct rather complicated large scale application circuits. Asynchronous circuit design has not been well established especially for large scale applications, then this library modules greatly support designers to realize their ideas with behavior-guaranteed module combination on handshake protocols. This library system is similar to the standard library system on the conventional synchronous ASIC design, where modules in the libraries are standardized and guaranteed for their proper operation. The design tools for PCA also developed to help for efficient and reliable designing on asynchronous circuits. This joint research project finished at March 2007 because appropriate killer applications have not been found and its performance has not been improved competitively with course grained reconfigurable devises such as FPGAs while the new concepts of PCA are attractive for future computing systems. For synchronous circuit design technology, we are now focusing on the higher level design circumstances, such as UML, SystemC, and other HDLs. We developed a new design flow from SFL (one of the HDLs) to SystemC for improving the design efficiency. As to the VDEC-based synchronous circuit technology, various applications such as bio-informatics and network security have been surveyed. We started a new approach to high performance computing systems with reconfigurable devices collaborating with the RIKEN research group, the PROGRAPE Project. The target of this project is Desktop Supercomputing System. Desktop means low-cost with commercially available FPGAs and PCs. We have been developing interface circuits and new applications such as fluid dynamics, data mining, and others. Members of the Computer Education Laboratory Prof. Kenichi Kuroda: Before his coming to this university, he belonged to the NTT laboratories and he was engaged with the research on superconductor devices, SAW devices, and X-ray optics. He joined this university mid 1995. He received his Dr. Eng. from Tokyo University in 1991. He had been a member of the Computer Device Lab for 5 years and moved to this lab in summer 2000. After coming to this university, he was interested in VLSI design technology. Especially, dynamically reconfigurable devices such as PCA (Plastic Cell Architecture) are the current major research direction. Prof. Junji Kitamichi: He received the B.S. and Ph.D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Centor at Osaka University, where he was assistant Professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. His research interests include formal methods for VLSI design, design verification, hardware description language, dynamical reconfigurable architectures, and real-time systems. Prof. Yuichi Okuyama: He was born in 1975. He received the M.S and Ph.D degrees in computer science and engineering from the University of Aizu in 1999 and 2002, respectively. He entered NTT Network Innovation Laboratories and was engaged with the development of PCA (Plastic Cell Architecture) devices. He joined the University of Aizu in 2005 as an assistant professor. His current interests are implementation of applications and tools for design automation on reconfigurable device(FPGA and other devices) and design of hardware for scientific calculations. Students : Research Topics Doctor Program Toshiyuki Ito : Processors on dynamically reconfigurable device PCA. Master Program : PCA related topics Tomoko Otsuka, Tomoyosi Kanno, Yasuhiro Sugita. Master Program : Application circuits and tool development Mitsuhiro Honda, Koji Ueda, Shuichi Watanabe. Shinya Iwazaki, Kazuya Misho, Noriaki Kaida, Hajime Katayama. Graduation Thesis Students : PCA related topics Shinya Iwazaki, Natsuki Chubachi, Kazuya Yokohari, Kazuya Misho. Graduation Thesis Students : Reconfigurable computing, application circuits and tool development Hayata Ikegami, Eisuke Ishikawa, Takahito Obara, Kaai Kojima, Anna Sato, Akihiro Shindo, Akira Takeuchi, Hidekazu Nagai, Tomohiro Nishikawa, Kota Fukuyo, Kenta Matsumoto, Yu Yamaki.

Refereed Proceeding Papers

[kitamiti-01:2006]	Kenichi Kuroda Kenji Asano, Junji Kitamichi. Proposal of Dynamic Module Library for System Level Modeling and Simulation ofDynamical Reconfigurable Systems. In 20th International Conference on VLSI DESIGN(VLSIDf07), pages 373.378, Jan. 2007.
	In this paper, we propose a library for the system level modeling andsimulation ofdynamically reconfigurable architectures(DRAs). Using the proposedlibrary, the designer can model the system specifications includingmodules for the dynamic generation and elimination thatare needed in the design of dynamically reconfigurable systems.In addition, we evaluate the proposed library by the modelingand simulation of sample circuits, such asmulti-context DRA and partially DRA. Using the proposedlibrary, we can model the system specifications as much the same amount asa detailed description, such as one using multiplexers and de-multiplexers.
[kuroken-01:2006]	Kenji Asano, Junji Kitamichi, and Kuroda Kenichi. Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems. In 20th Int. Natl. Conf. on VLSI Design. ACM, IEEE, Jan. 2007.
	In this paper, we propose a library for the system level modeling and simulation of dynamically reconfigurable architectures(DRAs). Using the proposed library, the designer can model the system specifications including modules for the dynamic generation and elimination that are needed in the design of dynamically reconfigurable systems. In addition, we evaluate the proposed library by the modeling and simulation of sample circuits, such as multi-context DRA and partially DRA. Using the proposed library, we can model the system specifications as much the same amount as a detailed description, such as one using multiplexers and de-multiplexers, which is a modeling formula for describing multi-context DRA. Under some conditions, higher-speed simulation is possible using the proposed library.

Unrefereed Papers

[kitamiti-02:2006]	Shuichi WATANABE, Junji KITAMICHI, Yuichi OKUYAMA, and Kenichi KURODA. A Hardware Algorithm for the Minimum pquasi Clique Cover Problem. In IEICE, editor, TECHNICAL REPORT OF IEICE Vol.106,No.389,VLD2006-84, pages 73.78. IEICE, IEICE, Nov. 2006.
	This paper proposes a hardware algorithm for the minimum p - quasi clique cover problem, and it isimplemented on FPGA. This problem is known as NP-complete and appears in the gene expression profile analysis.The reduction of the calculation time for this problem is important to accelerate the gene analysis. Our algorithmadopts a neural network for the reduction of the calculation time. Our architecture using a ring network can acceleratethe execution of our algorithm because all modules can execute in parallel independently. We show ourmethod is better than the existing methods in the searching ability of a solution and the calculation time.
[kitamiti-03:2006]	Junji Kitamichi Toshiyuki Ito, Yuuichi Okuyama and Kenichi Kuroda. A Proposal of Parallelism Changeable Processors on the Dynamically-Reconfigurable Device PCA. In In 28th PARTHENON Workshop, pages 55.64, June 2006.
	Recently, the program executed by general parallel-processing systems has multiple parallelisms. However the maximum parallelism of these processing systems is decided as some specific number in advance. In diverse processing situation, these systems with specific parallelism cause the situation of shortage- and excess-parallelism. This paper proposes the processor which can change its parallelism according to the programfs parallelism and instruction parallelism included in target program. In addition, we implemented the Instruction Level Parallel (ILP) processor, which is a fundamental element of the proposed processor, on dynamically reconfigurable real device PCA-1, and implemented an evaluation simulator using measurement values from the implemented processor. Using the simulator, we evaluated basic characteristics of the processor. From the result, we confirmed the existence of situations that the speed-up ratio surpasses the area-increase ratio in some condition.
[kitamiti-04:2006]	Yuichi Okuyama Junji Kitamichi Kazuya Misyou, Toshiyuki Ito and Kenichi Kuroda. Proposal of Adapted Load Balancing Model for Dynamically Reconfigurable Devices. In 2007 Tohoku-Section Joint Convention of Institutesof Electrical and Information Engineers, Japan, pages 1A.09, Aug. 2006.
	Dynamically reconfigurable devices canconstruct the feature-based architecture adapted to applicationsduring operations. This reconfigurability can improve the computational efficiency. An autonomous distributedprocessing has been proposed as a method of dataprocessing with use of the feature of these devices[1][2]. Inthis paper, we proposes an adapted load balancing processingsystem on these devices.The proposed load balancing process makes whole loadsequal by taking full advantage of hardware resources reallocation. This model executes parallel processing by distributingthe computation load. We explains about the conceptof proposed architecture.
[kitamiti-05:2006]	Koji UEDA Junji KITAMICHI Kenichi KURODA. System Level Modeling Method of Processor using SystemC. In 2007 Tohoku- Section Joint Convention of Institutesof Electrical and Information Engineers, Japan, pages 1A.10, Aug. 2006.
	Recently, a large scale system can be realizedon a chip like system LSI, since the advancedLSI manufacture technology has beendeveloped. As a result of increasing scale of LSI
[kitamiti-06:2006]	Junji Kitamiti Tomoyoshi Kanno, Yuichi Okuyama and Kenichi Kuroda. Implementation of a Resource Management System for FPGA based Computing. In 2007 Tohoku-Section Joint Convention of Institutesof Electrical and Information Engineers, Japan, pages 1A. 12, Aug. 2006.
	Field Programmable Gate Arrays (FPGAs) are devices that can configure circuits after fabrication. A merit of computing with FPGA is realization of high-speed processing such as the advanced digital signal processing and the numeric operating systems.We implemented a management system as shown in the diagram below. This system realizes FPGA based computing. Using this system for acceleration of processing, we should detect a part of programexecuted frequently and design circuits with the same function of the detected part. When the processes are executed, the circuits are configured on the FPGA for high performance.
[kitamiti-07:2006]	Kenichi Kuroda Eisuke Ishikawa, Junji Kitamichi. An Implementation of Butterfly Network on Partially Dynamically Reconfigurable FPGA. In IEICE, editor, Proceedings of the 2007 IEICE General Conference, pages D.18.4. IEICE, IEICE, March 2007.
[kitamiti-08:2006]	Shinya Iwazaki, Keigo Kurata, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Implementation of a Genetic Algorithm on Plastic Cell Architecture (PCA). In 2007 Tohoku-Section Joint Convention of Institutesof Electrical and Information Engineers, Japan, pages 2A.19, Aug. 2006.
	Genetic Algorithms (GAs) have excellent abilities in optimal solution searches. In contrast, GA processing speeds deteriorate in proportion to problem complexity. As one of the solutions of this problem, we can implement GAs on specific hardware (ASIC).However, GAs have parameters such as a gene length. The circuits scales of GAs on specific hardware depend on the gene length, and increase as the length is extended [1]. Therefore, it is difficult to change the gene length of GAs on specific hardware. In this paper, we implement GAs on hardware that does not depend on the gene length so as not to change circuits for changing the gene length. To verify above, we use Plastic Cell Architecture (PCA) that is a dynamically reconfigurable device.
[kitamiti-09:2006]	Junji KITAMICHI Noriaki KAIDA, Kouji UEDA and Kenichi KURODA. Modeling Method of Processors using UML and SystemC. In 2007 Tohoku-Section Joint Convention of Institutesof Electrical and Information Engineers, Japan, pages 2A.25, Apr. 2006.
	The scale of system designs is larger, more complicated.Shortening the development period andreducing manufacturing cost are demanded. In thispaper, we propose processor design method usingUML (Unified Modeling Language) which is one ofobject-oriented methods in software development.
[kuroken-02:2006]	Shinya Iwazaki, Keigo Kurata, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Implementation of a Genetic Algorithm on Plastic Cell Architecture (PCA). In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	Genetic Algorithms (GAs) have excellent abilities in optimal solution searches. In contrast, GA processing speeds deteriorate in proportion to problem complexity. As one of the solutions of this problem, we can implement GAs on specific hardware (ASIC). However, GAs have parameters such as a genelength. The circuits scales of GAs on specific hardware depend on the gene length, and increase as the length is extended [1]. Therefore, it is difficult to change the gene length of GAs on specific hardware. In this paper, we implement GAs on hardware that does not depend on the gene length so as not to change circuits for changing the gene length. To verify above, we use Plastic Cell Architecture (PCA) that is a dynamically reconfigurable device.
[kuroken-03:2006]	Shuichi WATANABE, Junji KITAMICHI, Yuichi OKUYAMA, and Kenichi KURODA. A Hardware Algorithm for the Minimum pquasi Clique Cover Problem. In Design Guia 2006 -IEICE Technical Report (VLD2006-84), pages 73.78. IEICE, 2006.
	This paper proposes a hardware algorithm for the minimum p - quasi clique cover problem, and it is implemented on FPGA. This problem is known as NP-complete and appears in the gene expression profile analysis. The reduction of the calculation time for this problem is important to accelerate the gene analysis. Our algorithm adopts a neural network for the reduction of the calculation time. Our architecture using a ring network can accelerate the execution of our algorithm because all modules can execute in parallel independently. We show our method is better than the existing methods in the searching ability of a solution and the calculation time.
[kuroken-04:2006]	Eisuke Ishikawa, Junji Kitamichi, and Kenichi Kuroda. An Implementation of Butterfly Network on Partially Dynamically Reconfigurable FPGA. In Proc. of IEICE Annual Conference 2006. IEICE, Mar. 2007.
	Implementation of Fast Butterfly Networks(BN) for reconfgurable devices is proposed. On BN, their parallelism is easily canged by use of flexibility of reconfigurability. We evaluate thier performance of implemented circuits on FPGAs.
[kuroken-05:2006]	Noriaki KAIDA, Kouji UEDA, Junji KITAMICHI, and Kenichi KURODA. Modeling Method of Processors using UML and SystemC. In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	The scale of system designs is larger, more complicated. Shortening the development period and reducing manufacturing cost are demanded. In this paper, we propose processor design method using UML (Unified Modeling Language) which is one of object-oriented methods in software development.
[kuroken-06:2006]	Toshiyuki ITO, Yuichi OKUYAMA, Junji KITAMICHI, and Kenichi KURODA. A Proposal of Parallelism Changeable Processors on the Dynamically-Reconfigurable Device PCA. In Proc. of 28th Parthenon Workshop, Jun. 2006.
	Recently, the program executed by general parallel-processing systems has multiple parallelisms. However the maximum parallelism of these processing systems is decided as some specific number in advance. In diverse processing situation, these systems with specific parallelism cause the situation of shortage- and excess-parallelism. This paper proposes the processor which can change its parallelism according to the programfs parallelism and instruction parallelism included in target program. In addition, we implemented the Instruction Level Parallel (ILP) processor, which is a fundamental element of the proposed processor, on dynamically reconfigurable real device PCA-1, and implemented an evaluation simulator using measurement values from the implemented processor. Using the simulator, we evaluated basic characteristics of the processor. From the result, we confirmed the existence of situations that the speed-up ratio surpasses the area-increase ratio in some condition.
[kuroken-07:2006]	Kazuya Misyou, Toshiyuki Ito, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Proposal of Adapted Load Balancing Model for Dynamically Reconfigurable Devices. In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	Dynamically reconfigurable devices can construct the feature-based architecture adapted to applications during operations. This reconfigurability can improve the computational efficiency. An autonomous distributed processing has been proposed as a method of data processing with use of the feature of these devices. In this paper, we proposes an adapted load balancing processing system on these devices. The proposed load balancing process makes whole loads equal by taking full advantage of hardware resources reallocation. This model executes parallel processing by distributing the computation load. We explains about the concept of proposed architecture.
[kuroken-08:2006]	Koji UEDA, Junji KITAMICHI, and Kenichi KURODA. System Level Modeling Method of Processor using SystemC. In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	Recently, a large scale system can be realized on a chip like system LSI, since the advanced LSI manufacture technology has been developed. As a result of increasing scale of LSI, the circuit design and its verification spends a lot of time. Therefore, the top-down design methods from system-level have been focused. In this paper, we describe a MIPS processor model using SystemC, one of system level design languages.
[kuroken-09:2006]	Tomoyoshi Kanno, Yuichi Okuyama, Junji Kitamiti, and Kenichi Kuroda. Implementation of a Resource Management System for FPGA based Computing. In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	Field Programmable Gate Arrays (FPGAs) are devices that can configure circuits after fabrication. A merit of computing with FPGA is realization of high-speed proc-essing such as the advanced digital signal processing and the numeric operating systems.We implemented a management system as shown in the diagram below. This system realizes FPGA based computing. Using this system for acceleration of proc-essing, we should detect a part of program executed fre-quently and design circuits with the same function of the detected part. When the processes are executed, the circuits are configured on the FPGA for high perform-ance.
[kuroken-10:2006]	Anna SATO, Yuichi OKUYAMA, Kenichi KURODA, Tsuyoshi HAMADA, Naoto NAKASATO, and Akihiko IBUKIYAMA. Error Evaluation of Arithmetic Circuit for One-dimensional SPH. In Proc. of IPSJ Tohoku Conference 2006. IPSJ, Jan. 2007
	Abstract In this research, the accuracy of numerical calculation of Hydrodynamics is evaluated for implementation on reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). The Smoothed Particle Hydrodynamics (SPH) method is used for the numeric calculation method representing fluid behavior by particle motion. It was proposed for modeling and problem solving in astrophysical phenomena and hydrodynamics. This paper examines calculation accuracy of the method on the shock tube problem and demonstrates the relation of mantissa accuracy and errors.
[kuroken-11:2006]	Tomohiro NISHIKAWA, Toshiyuki ITO, Yuichi OKUYAMAy, and Kenichi KURODA. Design of the LDPC decoder with variable redundant bit using sum-product algorithm. In Proc. of IPSJ Tohoku Conference 2006. IPSJ, Jan. 2007.
	Recently, the decoding process of the LDPC code is actively studied. Because the decoding process of the LDPC code can easily calculate and implement. Optimal circuit configuration, scale and circuit parallelism relate many parameters. For example, transmission quality, coding rate and bit error rate. This thesis focuses the coding rate of the LDPC code. I have created an automatic decoding architecture generator system according to the parity check matrix. I have designed the decoder of the LDPC code using the Verilog- HDL. Parameters of the program can easily change according to the parity check matrix. This system updates automatically the program according to the parity check matrix. This system can generate circuit of decoding architecture. I was able to decrease the executive working hours by the automatic generator system.
[kuroken-12:2006]	Toshiyuki Ito, Kazuya Mishou, Yuichi Okuyama, and Kenichi Kuroda. A Hardware Resource Management System for Adaptive Computing onDynamically Reconfigurable Devices. In Proc. of FCST2006. UoA, 2006.
	This paper proposes a realization method of the computer system with dynamical hardware-resource allocation on dynamically reconfigurable devices. The system consists of two or more parts and they can change the number of processing units according to each processing load. In the system, there is a competition problem between these parts. In order to solve this problem, we investigate required functions of resource management units on a simple processing model. This model is an adapted load balancing model consisting of an upper management unit, two management units and processing units shared by them.
[okuyama-01:2006]	ShuichiWATANABE, Junji KITAMICHI, Yuichi OKUYAMA, and Kenichi KURODA. A Hardware Algorithm for the Minimum pquasi Clique Cover Problem. In Design Guia 2006 -IEICE Technical Report (VLD2006-84), pages 73.78. IEICE, 2006.
	This paper proposes a hardware algorithm for the minimum p - quasi clique cover problem, and it is implemented on FPGA. This problem is known as NP-complete and appears in the gene expression profile analysis. The reduction of the calculation time for this problem is important to accelerate the gene analysis. Our algorithm adopts a neural network for the reduction of the calculation time. Our architecture using a ring network can accelerate the execution of our algorithm because all modules can execute in parallel independently. We show our method is better than the existing methods in the searching ability of a solution and the calculation time.
[okuyama-02:2006]	Shinya Iwazaki, Keigo Kurata, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Implementation of a Genetic Algorithm on Plastic Cell Architecture (PCA). In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	Genetic Algorithms (GAs) have excellent abilities in optimal solution searches. In contrast, GA processing speeds deteriorate in proportion to problem complexity. As one of the solutions of this problem, we can implement GAs on specific hardware (ASIC). However, GAs have parameters such as a genelength. The circuits scales of GAs on specific hardware depend on the gene length, and increase as the length is extended [1]. Therefore, it is difficult to change the gene length of GAs on specific hardware. In this paper, we implement GAs on hardware that does not depend on the gene length so as not to change circuits for changing the gene length. To verify above, we use Plastic Cell Architecture (PCA) that is a dynamically reconfigurable device.
[okuyama-03:2006]	Anna SATO, Yuichi OKUYAMA, Kenichi KURODA, Tsuyoshi HAMADA, Naoto NAKASATO, and Akihiko IBUKIYAMA. Error Evaluation of Arithmetic Circuit for One-dimensional SPH. In Proc. of IPSJ Tohoku Conference 2006. IPSJ, Jan. 2007.
	Abstract In this research, the accuracy of numerical calculation of Hydrodynamics is evaluated for implementation on reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). The Smoothed Particle Hydrodynamics (SPH) method is used for the numeric calculation method representing fluid behavior by particle motion. It was proposed for modeling and problem solving in astrophysical phenomena and hydrodynamics. This paper examines calculation accuracy of the method on the shock tube problem and demonstrates the relation of mantissa accuracy and errors.
[okuyama-04:2006]	Tomohiro NISHIKAWA, Toshiyuki ITO, Yuichi OKUYAMA, and Kenichi KURODA. Design of the LDPC decoder with variable redundant bit using sum-product algorithm. In Proc. of IPSJ Tohoku Conference 2006. IPSJ, Jan. 2007.
	Recently, the decoding process of the LDPC code is actively studied. Because the decoding process of the LDPC code can easily calculate and implement. Optimal circuit configuration, scale and circuit parallelism relate many parameters. For example, transmission quality, coding rate and bit error rate. This thesis focuses the coding rate of the LDPC code. I have created an automatic decoding architecture generator system according to the parity check matrix. I have designed the decoder of the LDPC code using the Verilog- HDL. Parameters of the program can easily change according to the parity check matrix. This system updates automatically the program according to the parity check matrix. This system can generate circuit of decoding architecture. I was able to decrease the executive working hours by the automatic generator system.
[okuyama-05:2006]	Toshiyuki Ito, Kazuya Mishou, Yuichi Okuyama, and Kenichi Kuroda. A Hardware Resource Management System for Adaptive Computing on Dynamically Reconfigurable Devices. In Proc. of FCST2006. UoA, 2006.
	This paper proposes a realization method of the computer system with dynamical hardware-resource allocation on dynamically reconfigurable devices. The system consists of two or more parts and they can change the number of processing units according to each processing load. In the system, there is a competition problem between these parts. In order to solve this problem, we investigate required functions of resource management units on a simple processing model. This model is an adapted load balancing model consisting of an upper management unit, two management units and processing units shared by them.
[okuyama-06:2006]	Tomoyoshi Kanno, Yuichi Okuyama, Junji Kitamiti, and Kenichi Kuroda. Implementation of a Resource Management System for FPGA based Computing. In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	Field Programmable Gate Arrays (FPGAs) are devices that can configure circuits after fabrication. A merit of computing with FPGA is realization of high-speed proc-essing such as the advanced digital signal processing and the numeric operating systems.We implemented a management system as shown in the diagram below. This system realizes FPGA based computing. Using this system for acceleration of proc-essing, we should detect a part of program executed fre-quently and design circuits with the same function of the detected part. When the processes are executed, the circuits are configured on the FPGA for high perform-ance.
[okuyama-07:2006]	Noriaki KAIDA, Kouji UEDA, Junji KITAMICHI, and Kenichi KURODA. Modeling Method of Processors using UML and SystemC. In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	The scale of system designs is larger, more complicated. Shortening the development period and reducing manufacturing cost are demanded. In this paper, we propose processor design method using UML (Unified Modeling Language) which is one of object-oriented methods in software development.
[okuyama-08:2006]	Toshiyuki ITO, Yuichi OKUYAMA, Junji KITAMICHI, and Kenichi KURODA. A Proposal of Parallelism Changeable Processors on the Dynamically-Reconfigurable Device PCA. In Proc. of 28th Parthenon Workshop, Jun. 2006.
	Recently, the program executed by general parallel-processing systems has multiple parallelisms. However the maximum parallelism of these processing systems is decided as some specific number in advance. In diverse processing situation, these systems with specific parallelism cause the situation of shortage- and excess-parallelism. This paper proposes the processor which can change its parallelism according to the programfs parallelism and instruction parallelism included in target program. In addition, we implemented the Instruction Level Parallel (ILP) processor, which is a fundamental element of the proposed processor, on dynamically reconfigurable real device PCA-1, and implemented an evaluation simulator using measurement values from the implemented processor. Using the simulator, we evaluated basic characteristics of the processor. From the result, we confirmed the existence of situations that the speed-up ratio surpasses the area-increase ratio in some condition.
[okuyama-09:2006]	Kazuya Misyou, Toshiyuki Ito, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Proposal of Adapted Load Balancing Model for Dynamically Reconfigurable Devices. In Proc. of Tohoku Joint Conference 2006. IEICE, IPSJ, Aug. 2006.
	Dynamically reconfigurable devices can construct the feature-based architecture adapted to applications during operations. This reconfigurability can improve the computational efficiency. An autonomous distributed processing has been proposed as a method of data processing with use of the feature of these devices. In this paper, we proposes an adapted load balancing processing system on these devices. The proposed load balancing process makes whole loads equal by taking full advantage of hardware resources reallocation. This model executes parallel processing by distributing the computation load. We explains about the concept of proposed architecture.

Grants

[kitamiti-10:2006]

Junji Kitamichi. Yayamori Foundation of Information Science Advancement, 2007-2008.

Academic Activities

[kitamiti-11:2006]	Kitamichi J., 2006. Member, IEEE
[kitamiti-12:2006]	Kitamichi J., 2006. Program Committee VLSI and Design Methodology Track Chairs, IEEE 7th International Conference on Computer and Information Technology(CIT)2007
[kitamiti-13:2006]	Kitamichi J., 2006. Member, IPS
[kitamiti-14:2006]	Kitamichi J., 2006. Member, IEICE
[kuroken-13:2006]	Kenichi Kuroda, 2006. JSAP Regular member
[kuroken-14:2006]	Kenichi Kuroda, 2006. IEICE Regular member
[kuroken-15:2006]	Kenichi Kuroda, 2006. IPSJ Regular member
[kuroken-16:2006]	Kenichi Kuroda, 2006. Member of IEICE Student Activity Support Committee
[kuroken-17:2006]	Kenichi Kuroda, 2006. Member of Management Board of PARTHENON Society (NPO)
[okuyama-10:2006]	Yuichi Okuyama, 2006. IEICE Regular member
[okuyama-11:2006]	Yuichi Okuyama, 2006. Steering Committee of PARTHENON Society (NPO)
[okuyama-12:2006]	Yuichi Okuyama, 2006. IPSJ Regular member

Ph.D, Master and Graduation Theses

[kitamiti-15:2006]	Hayata Ikegami. Graduation Thesis: Implementation of the CKY Algorithm on a Dynamically Reconfigurable Device, University of Aizu, 2006. Thesis Advisor: Kitamichi, J.
[kitamiti-16:2006]	Ishikawa Eisuke. Graduation Thesis: Implementation of Butterfly Network with Variable Parallelism on a Partially Reconfigurable Device, University of Aizu, 2006. Thesis Advisor: Kitamichi, J.
[kuroken-18:2006]	Kaai Kojima. Graduation Thesis: Arithmetic Precision of the Generalized Hebbian Algorithm for Hardware Implementation, University of Aizu, 2006.
[kuroken-19:2006]	Yuu Yamaki. Graduation Thesis: A Programming Framework for an NPC Algorithm inTurn-based Games, University of Aizu, 2006.
[kuroken-20:2006]	Yasuhiro Sugita. Master Thesis: Design of a Parallel Processing Modelwith Resource Management for PCA, University of Aizu, 2006. Thesis Advisor: Yuichi Okuyama.
[kuroken-21:2006]	Tomohiro Nishikawa. Graduation Thesis: Design of the LDPC decoder with variable redundant bits using the sum-product algorithm, University of Aizu, 2006.
[kuroken-22:2006]	Hidekazu Nagai. Graduation Thesis: An Execution Environment for a Logic Programming Language on PCA Using the Hopfield Neural Network, University of Aizu, 2006.
[kuroken-23:2006]	Koji Ueda. Master Thesis: System Level Design of a Dynamically Reconfigurable Processor, University of Aizu, 2006. Thesis Advisor: Junji Kitamichi.
[kuroken-24:2006]	Mitsuhiro Honda. Master Thesis: Formal Verification using Model Checking for Top-Down Digital Circuit Design, University of Aizu, 2006. Thesis Advisor: Junji Kitamichi.
[kuroken-25:2006]	Shuichi Watanabe. Master Thesis: A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem, University of Aizu, 2006. Thesis Advisor: Junji Kitamichi.
[kuroken-26:2006]	Tomoko Ootsuka. Master Thesis: Acceleration of Feed Forward Neural Networks on a Dynamically Reconfigurable Device PCA, University of Aizu, 2006. Thesis Advisor: Yuichi Okuyama.
[kuroken-27:2006]	Tomoyoshi Kanno. Master Thesis: A Resource Management System for Reconfigurable Computing, University of Aizu, 2006. Thesis Advisor: Yuichi Okuyama.
[okuyama-13:2006]	Tomoyoshi Kanno. Master Thesis: A Resource Management System for Reconfigurable Computing, University of Aizu, 2006. Supervisor: Kenichi kuroda, Thesis Advisor: Yuichi Okuyama
[okuyama-14:2006]	Tomoko Ootsuka. Master Thesis: Acceleration of Feed Forward Neural Networks on a Dynamically Reconfigurable Device PCA, University of Aizu, 2006. Supervisor: Kenichi kuroda, Thesis Advisor: Yuichi Okuyama
[okuyama-15:2006]	Akihiro Shindo. Graduation Thesis: Implementation of a Portable Exercise Environment using CD-Bootable OS, University of Aizu, 2006.
[okuyama-16:2006]	Yasuhiro Sugita. Master Thesis: Design of a Parallel Processing Model with Resource Management for PCA, University of Aizu, 2006. Supervisor: Kenichi kuroda, Thesis Advisor: Yuichi Okuyama
[okuyama-17:2006]	Kenta Matsumoto. Graduation Thesis: Implementation of PCI-X Interface Circuits on FPGA Boards for Particle Simulation, University of Aizu, 2006.
[okuyama-18:2006]	Takahito Obara. Graduation Thesis: An Execution Environmentfor Image Processing using FPGA, University of Aizu, 2006.
[okuyama-19:2006]	Akira Takeuchi. Graduation Thesis: Library Implementation for Visualization of Particlebased Fluid Simulation, University of Aizu, 2006.
[okuyama-20:2006]	Anna Sato. Graduation Thesis: Error Evaluation of Onedimensional SPH using Bit-variable Arithmetic Circuits, University of Aizu, 2006.

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