 |
 |
 |
 |
 |
Professor |
Visiting Professor |
Associate Professor |
Assistant Professor |
Research Associate |
- Die-hard sensor network
Related to this topic, the follwoing three works were done in 2006.
- Autonomous network structure creation: In sensor networks, a network
creation and a routing protocol are very important to transfer
the sensed data from each sensor node to a sink node or a base station
effectively. We developed an algorithm that can automatically create
a tree network structure whose root is the base station. Once the tree
structure is created, the structure is not collapsed easily even if some
sensor nodes die. In addition, a routing protocol is not needed explicitly,because the sensed data are naturally aggregated to the base station by
transferring the sensed data via the tree network structure.
- Sensor allocation method: A sensor allocation technique was proposed,
which can be applied to a sensor network constructed of many sensor
nodes having multiple sensors. The allocation problem is formulated as
a graph node coloring problem, and it can be solved by an autonomous
algorithm. This technique was also applied to the time slot allocation
in TDMA (time division multiple access) that is effective for the packet
collision avoidance.
- Autonomous network structure creation: In sensor networks, a network
creation and a routing protocol are very important to transfer
the sensed data from each sensor node to a sink node or a base station
effectively. We developed an algorithm that can automatically create
a tree network structure whose root is the base station. Once the tree
structure is created, the structure is not collapsed easily even if some
sensor nodes die. In addition, a routing protocol is not needed explicitly,because the sensed data are naturally aggregated to the base station by
transferring the sensed data via the tree network structure.
- Hardware design for an scalable array processor
Collaborated with the Operating System Laboratory in the University of Aizu, the hardware architecture of the scalable array processor dedicated to high-speed matrix-matrix operations was designed. In addition, the prototype system was implemented using FPGAs (Field Programmable Gate Arrays) to evaluate the feasibility of the architecture.
- Hardware for realistic image synthesis,
- Computer architecture for computer graphics,
- Reconfigurable hardware for multimedia applications, and
- Realtime systems for computer music
- Development of a CAD prototype
- Proposal of several optimization methods
- Parallel multithreaded processor architecture.
- Visual simulator for single cycle, multi-cycle and pipeline structure processors
by Java, C++.
- Trace-driven simulation tools for computer architecture design and performance
evaluation.
- Trace-driven simulation tools for computer architecture design and performance
evaluation.
|
The following researches are progressed in Computer Organization Laboratory: Toshiaki Miyazaki:
|
Refereed Journal Papers
| [miyazaki-01:2006] |
T. Murooka, A. Nagoya, T. Miyazaki, H. Ochi, and Y. Nakamura.
Network Processor for High-Speed Network and Quick Programming.
Journal of Circuits, Systems, and Computers (JCSC), World
Scientific, 16(1):65.79, 2007. |
| The paper describes the concept, architecture, and prototype test results of
a packet processor that enables us to implement an application-specific highspeed
packet processing system without expert-level programming skills. This
processor has a pipelined processing architecture and features coarse-grained
instructions that are based on the data formats of the telecommunication
packet. Using this processor, target applications can be implemented within a
short working period without degrading the processing performance.We implemented
a prototype system to evaluate its packet propagation delay and packet
forwarding performance. The measured results suggest that the architecture is
useful for packet processing on high-speed telecommunication networks. |
Refereed Proceeding Papers
| [miyazaki-02:2006] |
T. Miyazaki. Boolean Formulation for Sensor Allocation Problem
and Its Effective Solver. In ACM/IFIP/USENIX MidSensf06 (Internationl
Workshop on Middleware for Sensor Networks), pages 46.54,
Nov. 2006. |
| This paper proposes a sensor allocation technique that can be applied to a sensor
network constructed of many sensor nodes having multiple sensors. First, after
describing the sensor network model, the problem is formulated. The formulation
can handle the following two cases: (1) a minimum number of sensor nodes, and
(2) a maximum number of sensor nodes, each of which uses only one or a few
of its sensors. The formulation is based on 0-1 Integer Linear Programming.
A dedicated solver using a Binary Decision Diagram (BDD) is also described.
The proposed method can deal with the sudden death of a sensor and can
rapidly reproduce optimal solutions without the dead sensor. According to the
experimental results, all optimal and feasible solutions are obtained within 5
seconds in the case of 100 sensors. |
|
| [w-chu-01:2006] |
Yamin Li, Shietung Peng, andWanming Chu. K-MCore for Multicasting
on Mobile Ad Hoc Networks. In Shi-Jinn Horng and Chan-BiauYang, editors, Proceedings of the Seventh International Conference on
Parallel and Distributed Computing,Applications and Technologies (PDCATf
06), pages 109.114, Taipei, Taiwan, December 2006. IEEE, IEEE
Computer Society Press. |
| A k-cluster of a tree includes a single path and k-1 subpaths growing from
that path. A k-MCore is a k-cluster that minimizes the sum of the distances
of all vertices to the cluster plus the size of the cluster. This structure is motivated
by the applications on overlaymulticasting. The overlaymulticast protocol
constructs a virtual mesh spanning all member nodes of a multicast group. It
employs standard unicast routing and forwarding to fulfill multicast functionality.
In this paper, we propose effective distributed algorithms for constructing
k-MCore on a tree network. The k-MCore is more stable and easier to maintain
than the spanning tree in virtual mesh. The simulation results show that
our approach handles the flexibility and mobility issues in an overlay multicast
protocol effectively, especially when the group size is large. |
Unrefereed Papers
| [hiroshis-01:2006] |
H. Saito, T. Yoneda, and T. Nanya. Scheduling for Asynchronous
Circuits in Bundled-Data Implementation using Integer
Linear Programming. In IPSJ DA symposium 2006, pages 43.48,
2006. |
| [hiroshis-02:2006] |
N. Hamada nad T. Konishi, H. Saito, T. Yoneda, and T. Nanya.
Proposal of a Behavioral Synthesis Method for Asynchronous Circuits
in Bundled-data Implementation. In IEICE Technical Report,
pages 71.76, 2006. |
| [miyazaki-03:2006] |
and T. Miyazaki K. Onodera, R. Kawano. Autonomous Localtime
Synchronization Method forWireless Sensor Networks. In IPSJ
69th general conference, volume 4V-9, March 2007. |
| [miyazaki-04:2006] |
R. Kawano and K. Onodera and T. Miyazaki. Distributed
Algorithm to Sensor Function Allocation in Sensor Networks. In
IPSJ 69th general conference, volume 4V-8, March 2007. |
| [nisim-01:2006] |
Satoshi Nishimura. Overview of the SAMUEL concurrent scripting
language for real-time music information processing. In Research Report of the Information Processing Society of Japan, volume 2007-
MUS-69, pages 51.56, 2007. This paper introduces a concurrent scripting language named SAMUEL proposed by the author. SAMUEL is an object-oriented programming language designed for music data entry, algorithmic composition, research on music information processing, and programming education. It features concise description of concurrent processing and brief syntax for describing notes and rests with expressive information. The SAMUEL interpreter developed by the author, incorporating a real-time scheduler, is capable of timed control of MIDI synthesizers and interactive processing. |
Grants
| [hiroshis-03:2006] |
H. Saito. Ministry of Education Scientific Research Fund, 2006-
2008. |
| [miyazaki-05:2006] |
T. Miyazaki. Grant from the Support Center of Advanced
Telecommunications Technology Research (SCAT), 2006-2007. |
| [miyazaki-06:2006] |
T. Miyazaki. Commissioned Research Fund from NTT Laboratories,
2006. |
| [miyazaki-07:2006] |
T. Miyazaki. JSPS Grant-in-Aid for Scientific Research (No.
18500060), 2006-2008. |
Academic Activities
| [hiroshis-04:2006] |
H. Saito, 2006. Committee member, IPSJ SIGSLDM |
| [miyazaki-08:2006] |
T. Miyazaki, June 2006. Lecturer fFPGA technologies changing system designfin fSystem LSI design technologies coursef, IEICE Advanced Open Lecture Series |
| [miyazaki-09:2006] |
T. Miyazaki, 2005. Member, IPSJ |
| [miyazaki-10:2006] |
T. Miyazaki, 2006. Technical Program Committee Member, ACST2007 (The Third IASTED International Conference on Advances in Computer Science and Technology) |
| [miyazaki-11:2006] |
T. Miyazaki, 2005. Steering committee member, Technical Group for Reconfigurable Systems, IEICE |
| [miyazaki-12:2006] |
T. Miyazaki, 2006. Technical Program Committee Member, ISVLSI2006 (IEEE International Symposium on VLSI) |
| [miyazaki-13:2006] |
T. Miyazaki, 2006. Reviwer, The IPSJ Transactions on Advanced Computing Systems |
| [miyazaki-14:2006] |
Member, IEICE |
| [miyazaki-15:2006] |
T. Miyazaki, 2006. Technical Program Committee Member, RC education 2006 (International Workshop on Reconfigurable Computing Education) |
| [miyazaki-16:2006] |
T. Miyazaki, 2006. Reviwer, The IEICE Transactions |
| [miyazaki-17:2006] |
T. Miyazaki, 2005. Member, IEEE (CAS, ComSoc, CS) |
Ph.D, Master and Graduation Theses
| [hiroshis-05:2006] |
Miho Hoshi. Graduation Thesis: Evaluation of a Behavioral Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation, University of Aizu, 2006. Thesis Advisor: H. Saito |
| [hiroshis-06:2006] |
Syou Shimanuki. Graduation Thesis: A Design Method for Asynchronous Circuits in Bundled-Data Implementation on Field Programmable Gate Array, University of Aizu, 2006. Thesis Advisor: H. Saito |
| [hiroshis-07:2006] |
Yuuki Shiga. Graduation Thesis: Behavioral Synthesis of Asynchronous Circuits in Bundled-Data Implementation Considering Resource Bitwidth, University of Aizu, 2006. Thesis Advisor: H. Saito |
| [hiroshis-08:2006] |
Makoto Aoki. Graduation Thesis: A Synthesis Method of Speculative Completion for Asynchronous Circuits in Bundled-Data Implementation, University of Aizu, 2006. Thesis Advisor: H. Saito |
| [hiroshis-09:2006] |
Hiroyuki Shimizu. Graduation Thesis: Technology Mapping of Huffman Circuits on Field Programmable Gate Array, University of Aizu, 2006. Thesis Advisor: H. Saito |
| [hiroshis-10:2006] |
Vladislav Snegovoy. Master Thesis: Multivalued Logic Approach
to Fuzzy Controller Hardware Implementation, University of Aizu, 2006. Thesis Advisor: H. Saito |
| [hiroshis-11:2006] |
Implementation Using Capacitor Based Summing Amplifiers, University of Aizu, 2006. Thesis Advisor: H. Saito |
| [hiroshis-12:2006] |
Yasuhiko Murai. Master Thesis: Self-Timed Data Transmission
for Onchip Intermodular Communication, University of Aizu, 2006. Thesis Advisor: H. Saito |
| [miyazaki-18:2006] |
Yuu Ogio. Graduation Thesis: Improvement for Sensor Node
Synchronization based on Pulse-Coupled Oscillator Model, University of
Aizu, 2006. Thesis Advisor: T. Miyazaki |
| [miyazaki-19:2006] |
Isao Matsumoto. Graduation Thesis: Distributed Algorithms
for Clique Partitioning, University of Aizu, 2006. Thesis Advisor: T. Miyazaki |
| [miyazaki-20:2006] |
Yuka Sato. Graduation Thesis: FPGA Implementation of
Array Processor for High-speed Matrix Operastions, University of Aizu,
2006. Thesis Advisor: T. Miyazaki |
| [miyazaki-21:2006] |
Ryouhei Kawano. Graduation Thesis: Distributed Algorithm
to Allocate Sensor Function in Wireless Sensor Networks, University of
Aizu, 2006. Thesis Advisor: T. Miyazaki |
| [miyazaki-22:2006] |
Tatsuya Kasai. Graduation Thesis: An Over-the-Air Delivering
Method for Sensor Nodes, University of Aizu, 2006. Thesis Advisor: T. Miyazaki |
| [nisim-02:2006] |
Koji Itagaki. Master Thesis: Handling Sound Diffraction is Path Tracing, University of Aizu, 2007. Thesis Advisor: Satoshi Nishimura |
| [nisim-03:2006] |
Kozue Sawada. Master Thesis: Parallelization of multi-camera
area-based stereo matching, University of Aizu, 2007. Thesis Advisor: Satoshi Nishimura |
| [nisim-04:2006] |
Mitsuru Ito. Graduation Thesis: Depth of Field Extension by
Multiple Focused Images, University of Aizu, 2007. Thesis Advisor: Satoshi Nishimura |
| [nisim-05:2006] |
Hiroshi Hamao. Graduation Thesis: Integration of Real-Time Ray
Tracing on a Ray-Flow System, University of Aizu, 2007. Thesis Advisor: Satoshi Nishimura |
| [nisim-06:2006] |
Yoshinori Yoshida. Graduation Thesis: Feedback in the Samuel-
DSP Real-Time DSP Programming Environment, University of Aizu,
2007. Thesis Advisor: Satoshi Nishimura |
| [nisim-07:2006] |
Kyogo Yokota. Graduation Thesis: Analysis of Musical Expression by Statistics, University of Aizu, 2007. Thesis Advisor: Satoshi Nishimura |
Others
| [miyazaki-23:2006] |
T. Miyazaki. Visiting lecturer, The Tokyo University of Agriculture and Technology |
