Computer Education Laboratory

Kenichi Kuroda Professor	Junji Kitamichi Associate Professor	Yuichi Okuyama Assistant Professor	Ben A. Abderazek Assistant Professor

The academic area of the laboratory mainly covers computer design methodology. Educational course design for VLSI design, formal verification and reconfigurable computing are the major themes of this lab. Education: We have been developing an education program of VLSI design based on VDEC (VLSI Design and Education Center) support. VDEC offers various kinds of design tools without license costs and accepts chip fabrication orders in low price. This program was started as a joint research with Prof. Shima, who left from this university in 2004, in Computer Architecture Laboratory in 2001. Web-based manuals for HDL design, verification, and layout tools have been developed and are being updated depending on VDEC support tools every year. This year, as same as in 2006, we have been collaborating with Prof. Miyazaki who joined this university from April, 2005 at Computer Organization Lab. In 2007, members of our laboratory are four professors, 11 master program students, and 5 graduate thesis students. Among the above students, 3 entered the graduate school of our university and 2 students got jobs after graduation. Research: This year, we are now focusing on the higher level design circumstances, such as UML, SystemC, and other HDLs. We developed a new design ow from SFL (one of the HDLs) to SystemC for improving the design efficiency. As to the VDEC-based synchronous circuit technology, various applications such as bio-informatics and network security have been surveyed. We started a new approach to high performance computing systems with reconfigurable devices collaborating with the RIKEN research group, the PROGRAPE Project. The target of this project is Desktop Supercomputing System. Desktop means low-cost with commercially available FPGAs and PCs. We have been developing interface circuits and new applications such as uid dynamics, data mining, and others. We closed the research of PCA (Plastic Cell Architecture), which lasted for three years as the joint research project with NTT Laboratories. We collaborated a joint research with Applistar Corp. for medical image diagnostic system and got successful results. In autumn, we welcomed a new member of our lab., Ben Abdalha Abderazek, from the Univ. of Electro-Communications. Members of the Computer Education Laboratory Prof. Kenichi Kuroda: Before his coming to this university, he belonged to the NTT laboratories and he was engaged with the research on superconductor devices, SAW devices, and X-ray optics. He joined this university mid 1995. He received his Dr. Eng. from Tokyo University in 1991. He had been a member of the Computer Device Lab for 5 years and moved to this lab in summer 2000. After coming to this university, he was interested in VLSI design technology. Especially, dynamically reconfigurable devices such as PCA (Plastic Cell Architecture) are the current major research direction. Prof. Junji Kitamichi: He received the B.S. and Ph. D degrees in information and computer sciences from Osaka University, Japan, in 1988 and 1999, respectively. In 1991, he joined the Department of Information and Computer Sciences at Osaka University, Japan, as a research associate. From 1999 to 2002, he was with Cybermedia Centor at Osaka University, where he was assistant Professor. In 2002, he joined School of Computer Science and Engineering, the University of Aizu, Japan. His research interests include formal methods for VLSI design, design verification, hardware description language, dynamical reconfigurable architechtures, and real-time systems. Prof. Ben Abdallah Abderazek: He received his BTS degree from Sfax University in 1990. The BE, ME degrees from HUST Univ. in 1994 and 1997 respectively. In 2002, he received his Ph.D. degree from the Univ. of Electro-communications. From 2002 to 2007, he was a research associate at the Univ. of Electro-communications, Graduate School of Information Systems, then Assistant Professor at the network computing laboratory. He joined the Univ. of Aizu in 2007. His research interests span the areas of computer architecture, embedded systems, and VLSI. Prof. Yuichi Okuyama: He was born in 1975. He received the M. S and Ph. D degrees in computer science and engneering from the University of Aizu in 1999 and 2002, respectively. He entered NTT Network Innovation Laboratories and was engaged with the development of PCA (Plastic Cell Architecture) devices. He joined the University of Aizu in 2005 as an assistant professor. His crrent interests are implementation of applications and tools for disign automation on reconfigurable device(FPGA and other devices) and design of hardware for scientific calculations. Students : Master Program Shinya Iwazaki, Noriaki Kaida, Hajime Katayama, Kazuya Misho. Hayata Ikegami, Takahito Obara, Kaai Kojima, Anna sato, Akihiro Shindo, Tomohiro Nishikawa, Kenta Matsumoto.. Graduation Thesis Students: Fumiko Ohori, Daisuke Ohwada, Koichi Shibata, Takashi Hayashi, Kenji Mitome.

Refereed Journal Papers

[benab-01:2007]	M. Akanda, A. Ben Abdallah Abderazek, and M. Sowa. Dual-Execution Mode Processor Architecture for Embedded Applications. Journal of Mobile Multimedia, 03(04):347-370, 10 2007.
	Research paper
[benab-02:2007]	Yuuki Nakanisi, Arquimedes Canedo, Ben Abdallah Abderazek, and Sowa Masahiro. Optimizing Reaching Definitions Overhead in Queue Processors. Journal of Convergence Information technology, 02(04):36-40, 2007.
	Research Paper about QueueCore Compiler design.
[benab-03:2007]	A. Canedo, Ben Abdallah Abderazek, and M. Sowa. A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model. Journal of Computer Languages, Systems & Structures, 34(4):184-194, 10 2007.
	Research paper.
[benab-04:2007]	Ben Abdallah Abderazek, A. Canedo, T. Yoshinga, and S. Masahiro. The QC-2 Parallel Queue Processor Architecture. Journal of Parallel and Distributed Computing, 68(02):235 245, February 2008.
	Research work about a novel low power, low complexity processor architecture and preliminary design evaluation.
[benab-05:2007]	M. Akanda, Ben Abdallah Abderazek, and M. Sowa. Dual-Execution Mode Processor Architecture. Journal of Supercomputing, 44(2):103-125, 2 2008.
	Research paper about the design and evaluation of an embedded 32-bit processor architecture.
[kitamiti-01:2007, kuroken-01:2007]	Kenji Asano, Junji Kitamichi, and Kenichi Kuroda. Dynamic Module Library for System Level Modeling and Simulation of Dynamical Reconfigurable Systems. Journal of Computers, 3(2):55-62, 2008.
	In this paper, we propose a library for the system level modeling and simulation of the system which includes dynamically reconfigurable architectures(DRAs). The proposed library is an extended SystemC library. Using the proposed library, the designer can model the system specifications including modules for the dynamic generation and elimination and ports and channels for the dynamic connection and dispatch between them, that are needed in the design of general-purpose dynamically reconfigurable systems at the system design level. In addition, we evaluate the proposed library by the modeling and simulation of sample circuits, such as partially DRA and multi-context DRA. Using the proposed library, we can model the system specifications naturally and as much the same amount as a description, such as one using multiplexers and de-multiplexers, which is a modeling formula for describing multi-context DRA. Under some conditions, higher-speed simulation is possible using the proposed library.

Refereed Proceeding Papers

[benab-06:2007]	Arquimedes Canedo, Ben A. Abderazek, and S. Masahiro. Quantitative Evaluation of Common Subexpression Elimination on Queue Machines. In In proceedings of the International Symposium on Parallel Architectures, ISPAN 2008, pages 25-30, 2008.
	Research Paper keywords: Compiler Development
[benab-07:2007]	Ben A. Abderazek, M. Akanda, T. Yoshinaga, and M. Sowa. Mathematical Model for Multiobjective Synthesis of NoC Architectures. In IEEE, editor, Proc. of the 36th International Conference on Parallel Processing Workshops, volume -, page CD, IEEE, 09 2007. IEEE.
	Research paper about Network on Chip synthesis.
[benab-08:2007]	Arquimedes Canedo, Ben Abdallah Abderazek, and Masahiro Sowa. Queue Register File Optimization Algorithm for QueueCore Processor. In Proceedings of 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07), pages 169-176., 2007.
	Research paper
[kitamiti-02:2007, kuroken-02:2007]	Shuichi Watanabe, Junji Kitamichi, and Kenichi Kuroda. A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem. In 17th INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS(FPL 2007), pages 139-144, Jan. 2007.
	In this paper, we describe a hardware algorithm for the minimum p-quasi clique cover ( MPQCC) problem and its implementation on an FPGA. MPQCC problem is a combinational optimization problem that is NP-complete. Furthermore, gene expression profile analysis is one of applied fields of MPQCC problem. We aim to develop an inexpensive acceleration system using FPGAs for gene expression profile analysis. We adopt a Hopfield neural network for the proposed algorithm for the reduction of the calculation time. The proposed architecture using a ring network can execute the proposed algorithm effectively on FPGAs because each module can run in parallel independently and the system can be implemented with simple placement and routing of modules, and high scalability. We show that the proposed method is better than the existing one with regard to its solution searching ability and required calculation time.
[kitamiti-03:2007, kuroken-03:2007]	Koji Ueda Junji Kitamichi and Kenichi Kuroda. A Modeling of a Dynamically Reconfigurable Processor using SystemC. In 21st Int. Conf. on VLSI DESIGN 2008, pages 91-96, Jan. 2008.
	Recently, Dynamically Reconfigurable Processors (DRPs) have been proposed. In this paper, we describe a model of a DRP using a Dynamic Module Library (DML), which we have developed for the modeling of general-purpose dynamically reconfigurable systems. The DML is an extended SystemC library and enables the modeling of the dynamic generation and elimination of modules, ports and channels and the dynamic connection and dispatch between port and channel. Using the DML, we can model the DRP naturally. The architecture of the proposed DRP is based on an MIPS-type architecture and supports the instructions, which are for the dynamically reconfigurable operational units and for their generation and elimination. We describe the proposed DRP model and its evaluation results.

Unrefereed Papers

[kitamiti-04:2007, kuroken-04:2007]	Anna Sato, Naohito Nakasato, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Error Evaluation of One-dimensional SPH using Bit-variable Arithmetic Circuits. In Proceeding of 2007 Tohoku- Section Joint Convention of Institutes of Electrical and Information Engineers, pages 1A-19, Aug. 2007.
[kitamiti-05:2007, kuroken-05:2007]	Koji Ueda, Junji Kitamichi, and Kenichi Kuroda. A Modeling for Dynamically Reconfigurable Processor using SystemC. In Technical Report of IEICE Vol.107,No.31,VLD2007-4, pages 19-24, May 2007.
[kitamiti-06:2007, kuroken-06:2007]	Hayata Ikegami, Junji Kitamichi, Yuichi Okuyama, and Kenichi Kuroda. Modeling of an Embedded OS: Toppers/JSP Using UML. In Proceeding of 2008 Spring Annual Conference of IEICE, D-3-4, page 31, March 2008.
[kitamiti-07:2007, kuroken-07:2007]	Tomohiro Nishikawa, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Design of a LDPC decoder with variable redundant bits using the sum-product algorithm. In Proceeding of 2007 Tohoku- Section Joint Convention of Institutes of Electrical and Information Engineers, pages 1A-11, Aug. 2007.
[kitamiti-08:2007, kuroken-08:2007]	Kaai Kojima, Yuichi Okuyama, Junji Kitamichi, and Kenichi Kuroda. Arithmetic Precision of the Generalized Hebbian Algorithm for Hardware Implementation. In Proceeding of 2007 Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers, pages 1A-18, Aug. 2007.
[kitamiti-09:2007, kuroken-09:2007]	Kazuya Misho, Kenta Matsumoto, Yuichi Okuyama, Junji Kitamichi, Kenichi Kuroda, and Tsuyoshi Hamada. Implementation of a Resource Sharing Machine for an FPGA Computing System. In Proceeding of 31st PARTHENON Society, pages 51-57, Dec. 2007.
[kuroken-10:2007]	Daisuke Ohwada, Yuichi Okuyama, and Kenichi Kuroda. FPGA Implementation of Combined Autocorrelation Method for Real-time Tissue Elasticity Imaging. In Proceeding of 31th Parthenon WS, pages 45-50. NGO Parthenon Society, However, elasticity imaging methods are not suitable for real-time processing because of the amount of computation time they need. In this study, we implement the strain distribution estimation algorithm by spatial differentiation of the displacement distribution using the combined autocorrelation method (CA). The CA has advantages of producing high quality strain images with applicable to large displacements. We implement using SFL after evaluation on fixed point design using systemC. The implemented parallel-pipelined CA architecture on a Dini Group DNDVI DC board powerd by Virtex4 FX100 FPGA clocked at 100 MHz performs realtime processing at 30 fps. 2007.
[kuroken-11:2007]	Fumiko Ohori, Yuichi Okuyama, Kenichi Kuroda, and Tsuyoshi Hamada. Image Filter Processing Based on a Particle Simulation. In Pro- ceeding of 2007 4th Conference of Tohiku Branch of IPSJ, page No.11. IPSJ, Jan. 2008.
	Specific purpose processors can be used to build an accelerated calculator environment that is less expensive than supercomputers and can be used for scientific calculations and development of leading-edge technologies. These processors are certified for assisting various issues because this advanced hardware technologies can be introduced inexpensively. This thesis focuses on this advantage and presents image filter processing with one of the specific purpose processors. Image filter processing calculates with a specific purpose processor specialized in particle calculations, PROGRAPE-4. The study demonstrated the effective utilization by considering image filter processing as inter-particle calculations.

Books

[benab-09:2007]

A. Ben Abdallah. Multicore Systems on Chips. ISBN: 978-81-7895-258- 1. Signpost Publishers, 06 2007. Book

Grants

[kitamiti-10:2007]	Junji Kitamichi. The Telecommunications Advancement Foundation, 2008-2009.
[kuroken-12:2007]	Kenichi Kuroda. Joint Research with Applistar Corp., 2007.

Academic Activities

[benab-10:2007]	Ben Abdallah Abderazek, 2008. Member, IEEE computer
[benab-11:2007]	Kenichi Kuroda Ben Abdallah Abderaezk, Arquimedes Canedo. Processor for Mobile Applications, 09 2008. Book chapter.
[kitamiti-11:2007]	Kitamichi J., 2007. member, IEICE
[kitamiti-12:2007]	Kitamichi J., 2007. member, IPSJ
[kitamiti-13:2007]	Kitamichi J., 2007. member. IEEE
[kuroken-13:2007]	Kenichi Kuroda, 2006. JSAP Regular member
[kuroken-14:2007]	Kenichi Kuroda, 2006. IEICE Regular member
[kuroken-15:2007]	Kenichi Kuroda, 2006. IPSJ Regular member
[kuroken-16:2007]	Kenichi Kuroda, 2006. Member of IEICE Student Activity Support Committee
[kuroken-17:2007]	Kenichi Kuroda, 2006. Member of Management Board of PARTHENON Society (NPO)

Patents

Ph.D, and Others Theses

[benab-12:2007]

Ben Abdallah Abderazek. Queue Processor Architecture Based on Circular-Queue-Register, 11 2008.

[kuroken-18:2007]	Takashi Hayashi. Graduation Thesis: Implementation of Digital Audio Signal Processing Circuits on FPGAs, University of Aizu, 2007. Thesis Advisor: Kenichi Kuroda
[kuroken-19:2007]	Kenji Mitome. Effectiveness Assessment of the PCI Express Interface on an FPGA Computing System, University of Aizu, 2007. Thesis Advisor: Yuichi Okuyama
[kuroken-20:2007]	Kazuya Misyo. Master Thesis: Design and Implementation of Resource Management System for FPGA Computing, University of Aizu, 2007. Thesis Advisor: Yuichi Okuyama
[kuroken-21:2007]	Kouichi Shibata. Implementation of Variable-Precision Trigonometrical Functions for Digital Signal Processing on FPGA, University of Aizu, 2007. Thesis Advisor: Yuichi Okuyama
[kuroken-22:2007]	Fumiko Ohori. Graduation Thesis: Image Filter Processing Based on a Particle Simulator, University of Aizu, 2007. Thesis Advisor: Yuichi Okuyama
[kuroken-23:2007]	Kouichi Shibata. Implementation of Variable-Precision Trigonometrical Functions for Digital Signal Processing on FPGA, University of Aizu, 2007. Thesis Advisor: Yuichi Okuyama
[kuroken-24:2007]	Hajime Katayama. Master Thesis: Development of an Architecture Level Simulator for a Tile Processor, RapidMatriX, University of Aizu, 2007. Thesis Advisor: Yuichi Okuyama
[kuroken-25:2007]	Daisuke Ohwada. Implementation of a Combined Autocorrelation Method for Real-time Tissue Elasticity Imaging on FPGA, University of Aizu, 2007. Thesis Advisor: Yuichi Okuyama
[kuroken-26:2007]	Shinya Iwazaki. Master Thesis: An Acceleration Method for Object Recognition and Image Segmentation Using 2DCDP, University of Aizu, 2007. Thesis Advisor: Kenichi Kuroda

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