Professor 
Associate Professor 
Assistant Professor 
Tsuneo Tsukahara:

[kohira01:2009] 
Y. Tomioka, Y. Kurata, Y. Kohira, and A. Takahashi. MILPbased
Efficient Routing Method with Restricted Route Structure for 2Layer Ball
Grid Array Packages. IEICE Trans. Fundamentals, E92A(12):2998 E006,
2009. 
In this paper, we propose a routing method for 2layer ball grid array packages that
generates a routing pattern satisfying a design rule. In our proposed method, the
routing structure on each layer is restricted while keeping most of feasible patterns
to efficiently obtain a feasible routing pattern. A routing pattern that satisfies the
design rule is formulated as a mixed integer linear programming. In experiments with
seven data, we obtain a routing pattern such that satisfies the design rule within a
practical time by using a mixed integer linear programming solver. 

[kohira02:2009] 
Y. Kohira, S. Tani, and A. Takahashi. Minimization of Delay Insertion
in Clock Period Improvement in GeneralSynchronous Framework. IEICE
Trans. Fundamentals, E92A(4):1106 E114, 2009. 
In generalsynchronous framework, in which the clock is distributed periodically to
each register but not necessarily simultaneously, the circuit performance such as
the clock period is expected to be improved by delay insertion. However, if the
amount of inserted delays is too much, then the circuit is changed too much and the
circuit performance might not be improved. In this paper, we propose an efficient
delay insertion method that minimizes the amount of inserted delays in the clock
period improvement in generalsynchronous framework. In the proposed method,
the amount of inserted delays is minimized by using an appropriate clock schedule
and by inserting delays into appropriate places in the circuit. Experiments show that
the proposed method can obtain optimum solutions in short time in many cases. 

[kohira03:2009] 
Y. Kohira, S. Suehiro, and A. Takahashi. A Fast Longer Path Algorithm
for Routing Grid with Obstacles using Biconnectivity based Length Upper
Bound. IEICE Trans. Fundamentals, E92A(12):2971 E978, 2009. 
In recent VLSI systems, signal propagation delays are requested to achieve the specifications
with very high accuracy. In order to meet the specifications, the routing
of a net often needs to be detoured in order to increase the routing delay. A routing
method should utilize a routing area with obstacles as much as possible in order to
realize the specifications of nets simultaneously. In this paper, a fast longer path algorithm
that generates a path of a net in routing grid so that the length is increased
as much as possible is proposed. In the proposed algorithm, an upper bound for the
length in which the structure of a routing area is taken into account is used. Experiments
show that our algorithm utilizes a routing area with obstacles efficiently. 
[fujii01:2009] 
R.H. Fujii and T. Hayashi. Learning and Recognition of Similar Temporal
Sequences. In Conference Organizers, editor, 2009 International Midwest
Symposium on Circuits and Systems, pages 885 E888. IEEE, IEEE, August
2009. 
Learning and recognition of object velocity sequences using a hierarchical network similar
in structure to the mammalian neocortex is proposed. Space and time invariant
representations of velocity sequences are captured in an unsupervised manner. 

[kohira04:2009] 
In this paper, we propose CAFE router which obtains routes of multiple nets with
target wire lengths for single layer routing grid with obstacles. CAFE router extends
the route of each net from a pin to the other pin greedily so that the wire length of the
net approaches its target wire length. Experiments show that CAFE router obtains the
routes of nets with small length error in short time. 
[kohira05:2009] 
N. Takahashi, Y. Tomioka, Y. Kohira, and A. Takahashi. Fast Estimation
of Peak Power by Appropriate Input Vector Selection. In DA symposium
2009, pages 13 E8, August 2009. 
[kohira06:2009] 
N. Takahashi, Y. Tomioka, Y. Kohira, and A. Takahashi. Fast Estimation
Method of Peak Power considering Input Vector and Inner State of
a Circuit. In IEICE Technical Report (VLD2009115), volume 109, pages
97 E02, March 2010. 
[kohira07:2009] 
Y. Kohira and A. Takahashi. Clustering Method for Low Power
Clock Tree in General Synchronous Framework. In IEICE Technical Report
(VLD2009119), volume 109, pages 121 E26, March 2010. 
[kohira08:2009] 
Y. Kohira and A. Takahashi. A Wall Generation for Trunk Routing of
Multiple Nets on Single Layer. In IEICE Technical Report (VLD200931),
volume 109, pages 13 E8, September 2009. 
[kohira09:2009] 
Y. Kohira and A. Takahashi. A River Routing Method for Single Layer
with Obstacles by Area Partition. In the 2009 IEICE Society Conference,
volume A, page 58, September 2009. 
[kohira10:2009] 
K. Shinoda, Y. Kohira, and A. Takahashi. Octilinear Routing Method
with Congestion Relaxation by Slant Lines. In IEICE Technical Report
(VLD200923), volume 109, pages 97 E02, July 2009. 
[kohira11:2009] 
M. Inoue, Y. Tomioka, Y. Kohira, and A. Takahashi. A RST Construction
Method for Vertices with Maximum Path Length. In IEICE Technical
Report (VLD20094), volume 109, pages 31 E6, May 2009. 
[tsuka01:2009] 
H. Ito and T. Tsukahara. Cascaded PolyPhase Filters with Amplification
using InterStage SourceFollower Buffers. In IEICE General Conference.
IEICE, March 2010. 
[tsuka02:2009] 
T. Tsukahara. History and Technology Trends of Si RF Analog LSI
Developments EEEmergence of NewType Circuit Designers EE In IEICE
Tecnical Report, ICD. IEICE, Dec. 2009. 
[tsuka03:2009] 
T. Tsukahara, S. Izumi, and T. Yoshida. Research of IF Circuits for
SpectrumAnalyzing Receivers. In IEICE Technical Report on Silicon Analog
RF Technologies. IEICE, July 2009. 
[tsuka04:2009] 
T. Tsukahara. Design of CMOS RF Circuits. MARUZEN, Nov. 2009.
We describe basics on CMOS RF circuit design. This book covers from RFsystem
overview to CMOS RF circuits, which is suitable for guraduate students and practicing
engineers. 
We describe basics on CMOS RF circuit design. The first volume presents RF system
design. Then, the second to fourth volumes explain design of onchip inductors, amplifiers
and mixers, and VCOs. Finally, the fifth volume describes design of an lowIF
receiver. 
[kohira12:2009] 
Y. Kohira. Cooperative Research Fund from the University of Kitakyushu,
2009. 
[kohira13:2009] 
Y. Kohira. Commissioned Research Fund from Fujitsu Laboratories
Ltd., 2009. 
[tsuka05:2009] 
T. Tsukahara. Commisioned Research Fund from ADVANTEST Corporation,
2009. 
[tsuka06:2009] 
T. Tsukahara. Cooperative Research Fund from NTT Network Innovation
Labs, 2009. 
[tsuka07:2009] 
T. Tsukahara, 2009. Member of the IEICE Electronics Society Technical Committee on Integrated Circuits and Devices 
[fujii02:2009] 
Kosuke Tanaka. Graduation Thesis: Stable Bipedal Robot Walk, University
of Aizu, 2009.
of Object Velocity, University of Aizu, 2009. Thesis Advisor: R. H. Fujii 
[fujii03:2009] 
Kosuke Tanaka. Graduation Thesis: Stable Bipedal Robot Walk, University
of Aizu, 2009.
of Object Velocity, University of Aizu, 2009. Thesis Advisor: R. H. Fujii 
[fujii04:2009] 
Tomohiro Tadano. Graduation Thesis: Electroactive Polymer (EAP)
Actuator for Robotics, University of Aizu, 2009. Thesis Advisor: R. H. Fujii 
[fujii05:2009] 
Takahiro Sekine. JGraduation Thesis: apanese Alphabet Sound Recognition
Using a Neocortexlike Network, University of Aizu, 2009. Thesis Advisor: R. H. Fujii 
[fujii06:2009] 
Satoshi Wagatsuma. Graduation Thesis: Bipedal Robot Control for Reflex
Motions, Recovery from Falls, and Soccer Ball Kick, University of Aizu,
2009. Thesis Advisor: R. H. Fujii 
[tsuka08:2009] 
Akifumi Hosoya. Graduation Thesis: Reduction of Intermodulation Distortion
in Bipolar and MOS Mixers using Parallel Differential Pairs, University
of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara 
[tsuka09:2009] 
Mitsuru Suzuki. Graduation Thesis: Noise Canceling Techniques for
LowNoise Amplifiers, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara 
[tsuka10:2009] 
Takahiro Tsushima. Graduation Thesis: An Analysis of a Quadrature
Mixer and a Proposal of PhaseError Compensation Designs in HighFrequency
Regions, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara 
[tsuka11:2009] 
Saeko Yoshinari. Graduation Thesis: An Architectural Study of a Low
Power LMV (LNA, Mixer and VCO) Cell, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara 
[tsuka12:2009] 
Hidekazu Usui. Master Thesis: A CurrentMode Sampler with an Embedded
Filter Function for Wireless Systems, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara 
[tsuka13:2009] 
Tadahiro Yoshida. Master Thesis: A Receiver Using Subsampling and
Fourier Transform for SoftwareDefined Radio Systems, University of Aizu, Feb.
2010. Thesis Advisor: T. Tsukahara 
[tsuka14:2009] 
Yuske Sato. Graduation Thesis: An Analysis of Distortion Canceling
Methods for LowNoise Amplifiers, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara 
[tsuka15:2009] 
Akio Ogino. Master Thesis: Broadband Design of a Windowed Integration
Sampler (WIS) Filter with Linearphase Characteristics, University of
Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara 
[tsuka16:2009] 
Kazuya Takahashi. Graduation Thesis: Wideband Design Techniques
for LowNoise Amplifiers, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara 
[tsuka17:2009] 
T. Tsukahara. Seminar: Design Examples and Perspective of Analog RF CMOS Circuits, June 23 2009 and Jan. 22 2010 