Computer Logical Design Laboratory

Tsuneo Tsukahara Professor	Robert H. Fujii Associate Professor	Yukihide Kohira Assistant Professor

Tsuneo Tsukahara: Software-Defined Radio Receivers Related to this topic, the following work was done in 2009. A Spectrum-Analyzing Method for Multi-band Wireless Transceivers: Recently the demand for wireless systems such as sensor networks has been rapidly growing. However, radio-wave resources are limited and invaluable especially in these days. Therefore, a software-defied radio (SDR) and a cognitive radio, which is a principal application of SDR, can be the key to greatly improving frequencyspectrum efficiency. SDRs demand flexibility and reconfigurability in RF (Radio Frequency) circuits. Therefore, a frequency-efficient wireless transceiver architecture is indispensable. In 2009, we proceeded to the analysis and design of a multi-band wireless transceiver using a spectrum-analyzing method and verified usefulness of this architecture using mainly system and circuit simulators with Rohm 0.18um-CMOS parameters. In a receive mode, radio frequency (RF) signals are first amplified and converted to intermediate frequency (IF) signals less than about 10 MHz using mixers or frequency converters. In a spectrum-analyzing method, we use Fourier transform of IF signals in the analog-signal domain because undesired strong signals should be attenuated before analog to digital (A/D) converters to save the number of resolution bits of A/D converters. The Fourier transform are performed using an analog multiplier and an integrator. RF/IF building blocks we designed have three features as follows: We applied windowed integration sampler (WIS) to the IF Fourier transform integration. The WIS also shows filtering with the sinc function. Low-distortion and wideband techniques are devised for RF low-noise amplifiers and mixers. A high-precision quadrature modulator is newly devised, which features localoscillator (LO) phase-error compensation. Robert Fujii: Neural Networks Due to the amazingly complex and numerous neural connections and the huge number of neurons present in the brain, only phenomenological system level notions about the workings of an entire mammalian brain are currently known. At the brain sub-system level, biologists and computational neural scientists have been somewhat successful at modeling brain regions such as the hippocampus and the auditory nerve system using mathematical models and simplified neuron models such as chaotic attractor and integrate and fire neuron based neural networks. At the lowest brain system level, biologically and physically realistic brain modelers have used very detailed neuron models (e.g. Hodgkin and Huxley model) to simulate the behavior of small neural networks; however, the very fact that detailed physiologically realistic neuron models were used has made it difficult to build larger neural networks whose behavior could be analyzed properly. Research was carried out in three directions: Invariant learning using the hierarchical, parallel, and distributed organization model of the biological neocortex for the recognition of spoken hiragana sound. Analysis of feedback spiking neural networks for sequence detection. Development of a spiking neural network simulator. Future work in the neural networks area will include:a) development of a neural system capable of spoken word recognition; b) a mathematical model of the rhythmic coupling that occurs in biological neurons; c) an event driven spiking neural network simulator capable of accurately simulating recurrent networks; and d) small-scale analog circuit analysis and design of recurrent spiking neural networks. Robotics Research in the area of autonomous,intelligent,and interactive robotics for the home or in a work environment is gaining momentum. Research and development work in the areas of bi-pedal robot real-time locomotion control was carried out. The bi-pedal robot that was used is approximately 50cm tall and is equipped with 22 servo motors, a camera, and a 3-axis accelerometer. A pico-size motherboard equipped with a 1 GHz Atom ( Intel ) processor, the Linux (Ubuntu)operating system with real-time patches, and a notebook PC connected serially to the picosize motherboard ( for image processing) were used for the control of the robot. Relatively stable bi-pedal robot locomotion ( fast and slow walk, turn, walking backwards, walking sideways) was achieved using a 3D accelerometer sensor and multi-thread processing routines. Recovering from falls and kicking a small soccer ball straight ahead and side-ways were also achieved. A small two-wheel robot that used inverted pendulum control to maintain stability was developed. Future research includes: a) stable and autonomous two-wheeled locomotion on various terrains; and b) control of a one-wheeled robot. A new type of robot actuator based on ion movement inside a polymer membrane was investigated. This type of actuator is relatively soft, lightweight, has no moving mechanical components like gears, can be as strong as muscles, and consumes very low power. The actuator that was fabricated showed good strain but its life cycle was limited to a few hours of operation. Future research includes: a) actuator operation in a liquid as well as dry environment; b) long life cycle; c) development of an actuator that can develop a large force; and d) development of xsa simple and low cost actuator fabrication process. Yukihide Kohira: Design Automation Methodology for LSI Circuits Due to the increase of scales of LSI circuits and the decrease of time to market of LSI products, LSI designers use design automation systems in order to design LSI circuits. Since the performance of LSI product depends heavily on the used design automation systems, the importance of researching design automation has been increased. Our research interests are design automation methodology in general-synchronous framework and routing method for PCB design. General-synchronous Framework In the conventional clock synchronous framework which is adopted in most circuits, a clock is distributed to all registers periodically and simultaneously. In this framework, many issues have been pointed out. On the other hand, in general-synchronous framework, a clock is distributed periodically to all registers but the clock is not necessarily distributed simultaneously. General-synchronous framework is expected to give essential solutions for the issues in the conventional clock synchronous framework with low introduction costs since circuits can be improved by modifying only clock circuits to satisfy clock schedules in which circuits work correctly. The target of our research is to establish a design automation system which can design LSI circuits in general-synchronous framework which satisfy with required circuit performance ash as high frequency, low power, and so on. PCB routing Due to the increase of operation frequency, signal propagation delay is requested to achieve a specification with very high accuracy. In PCB routing, the signal propagation delay of the net is controlled by controlling its wire length. We investigate routing methods which obtain routes whose target lengths are realized with high accuracy in single-layer. The goal of our research is to establish a routing methodology which can be applied to any PCB routing problems such as multi-layer, multi-terminal, and so on.

Refereed Journal Papers

[kohira-01:2009]	Y. Tomioka, Y. Kurata, Y. Kohira, and A. Takahashi. MILP-based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundamentals, E92-A(12):2998 E006, 2009.
	In this paper, we propose a routing method for 2-layer ball grid array packages that generates a routing pattern satisfying a design rule. In our proposed method, the routing structure on each layer is restricted while keeping most of feasible patterns to efficiently obtain a feasible routing pattern. A routing pattern that satisfies the design rule is formulated as a mixed integer linear programming. In experiments with seven data, we obtain a routing pattern such that satisfies the design rule within a practical time by using a mixed integer linear programming solver.
[kohira-02:2009]	Y. Kohira, S. Tani, and A. Takahashi. Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework. IEICE Trans. Fundamentals, E92-A(4):1106 E114, 2009.
	In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, the circuit performance such as the clock period is expected to be improved by delay insertion. However, if the amount of inserted delays is too much, then the circuit is changed too much and the circuit performance might not be improved. In this paper, we propose an efficient delay insertion method that minimizes the amount of inserted delays in the clock period improvement in general-synchronous framework. In the proposed method, the amount of inserted delays is minimized by using an appropriate clock schedule and by inserting delays into appropriate places in the circuit. Experiments show that the proposed method can obtain optimum solutions in short time in many cases.
[kohira-03:2009]	Y. Kohira, S. Suehiro, and A. Takahashi. A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound. IEICE Trans. Fundamentals, E92-A(12):2971 E978, 2009.
	In recent VLSI systems, signal propagation delays are requested to achieve the specifications with very high accuracy. In order to meet the specifications, the routing of a net often needs to be detoured in order to increase the routing delay. A routing method should utilize a routing area with obstacles as much as possible in order to realize the specifications of nets simultaneously. In this paper, a fast longer path algorithm that generates a path of a net in routing grid so that the length is increased as much as possible is proposed. In the proposed algorithm, an upper bound for the length in which the structure of a routing area is taken into account is used. Experiments show that our algorithm utilizes a routing area with obstacles efficiently.

Refereed Proceeding Papers

[fujii-01:2009]	R.H. Fujii and T. Hayashi. Learning and Recognition of Similar Temporal Sequences. In Conference Organizers, editor, 2009 International Midwest Symposium on Circuits and Systems, pages 885  E888. IEEE, IEEE, August 2009.
	Learning and recognition of object velocity sequences using a hierarchical network similar in structure to the mammalian neocortex is proposed. Space and time invariant representations of velocity sequences are captured in an unsupervised manner.
[kohira-04:2009]	In this paper, we propose CAFE router which obtains routes of multiple nets with target wire lengths for single layer routing grid with obstacles. CAFE router extends the route of each net from a pin to the other pin greedily so that the wire length of the net approaches its target wire length. Experiments show that CAFE router obtains the routes of nets with small length error in short time.

Unrefereed Papers

[kohira-05:2009]	N. Takahashi, Y. Tomioka, Y. Kohira, and A. Takahashi. Fast Estimation of Peak Power by Appropriate Input Vector Selection. In DA symposium 2009, pages 13 E8, August 2009.
[kohira-06:2009]	N. Takahashi, Y. Tomioka, Y. Kohira, and A. Takahashi. Fast Estimation Method of Peak Power considering Input Vector and Inner State of a Circuit. In IEICE Technical Report (VLD2009-115), volume 109, pages 97 E02, March 2010.
[kohira-07:2009]	Y. Kohira and A. Takahashi. Clustering Method for Low Power Clock Tree in General Synchronous Framework. In IEICE Technical Report (VLD2009-119), volume 109, pages 121 E26, March 2010.
[kohira-08:2009]	Y. Kohira and A. Takahashi. A Wall Generation for Trunk Routing of Multiple Nets on Single Layer. In IEICE Technical Report (VLD2009-31), volume 109, pages 13 E8, September 2009.
[kohira-09:2009]	Y. Kohira and A. Takahashi. A River Routing Method for Single Layer with Obstacles by Area Partition. In the 2009 IEICE Society Conference, volume A, page 58, September 2009.
[kohira-10:2009]	K. Shinoda, Y. Kohira, and A. Takahashi. Octilinear Routing Method with Congestion Relaxation by Slant Lines. In IEICE Technical Report (VLD2009-23), volume 109, pages 97 E02, July 2009.
[kohira-11:2009]	M. Inoue, Y. Tomioka, Y. Kohira, and A. Takahashi. A RST Construction Method for Vertices with Maximum Path Length. In IEICE Technical Report (VLD2009-4), volume 109, pages 31 E6, May 2009.
[tsuka-01:2009]	H. Ito and T. Tsukahara. Cascaded Poly-Phase Filters with Amplification using Inter-Stage Source-Follower Buffers. In IEICE General Conference. IEICE, March 2010.
[tsuka-02:2009]	T. Tsukahara. History and Technology Trends of Si RF Analog LSI Developments �E�EEmergence of New-Type Circuit Designers �E�E In IEICE Tecnical Report, ICD. IEICE, Dec. 2009.
[tsuka-03:2009]	T. Tsukahara, S. Izumi, and T. Yoshida. Research of IF Circuits for Spectrum-Analyzing Receivers. In IEICE Technical Report on Silicon Analog RF Technologies. IEICE, July 2009.

Books

[tsuka-04:2009]	T. Tsukahara. Design of CMOS RF Circuits. MARUZEN, Nov. 2009. We describe basics on CMOS RF circuit design. This book covers from RF-system overview to CMOS RF circuits, which is suitable for guraduate students and practicing engineers.
	We describe basics on CMOS RF circuit design. The first volume presents RF system design. Then, the second to fourth volumes explain design of on-chip inductors, amplifiers and mixers, and VCOs. Finally, the fifth volume describes design of an low-IF receiver.

Grants

[kohira-12:2009]	Y. Kohira. Cooperative Research Fund from the University of Kitakyushu, 2009.
[kohira-13:2009]	Y. Kohira. Commissioned Research Fund from Fujitsu Laboratories Ltd., 2009.
[tsuka-05:2009]	T. Tsukahara. Commisioned Research Fund from ADVANTEST Corporation, 2009.
[tsuka-06:2009]	T. Tsukahara. Cooperative Research Fund from NTT Network Innovation Labs, 2009.

Academic Activities

[tsuka-07:2009]

T. Tsukahara, 2009. Member of the IEICE Electronics Society Technical Committee on Integrated Circuits and Devices

Ph.D, Master and Graduation Theses

[fujii-02:2009]	Kosuke Tanaka. Graduation Thesis: Stable Bipedal Robot Walk, University of Aizu, 2009. of Object Velocity, University of Aizu, 2009. Thesis Advisor: R. H. Fujii
[fujii-03:2009]	Kosuke Tanaka. Graduation Thesis: Stable Bipedal Robot Walk, University of Aizu, 2009. of Object Velocity, University of Aizu, 2009. Thesis Advisor: R. H. Fujii
[fujii-04:2009]	Tomohiro Tadano. Graduation Thesis: Electro-active Polymer (EAP) Actuator for Robotics, University of Aizu, 2009. Thesis Advisor: R. H. Fujii
[fujii-05:2009]	Takahiro Sekine. JGraduation Thesis: apanese Alphabet Sound Recognition Using a Neocortex-like Network, University of Aizu, 2009. Thesis Advisor: R. H. Fujii
[fujii-06:2009]	Satoshi Wagatsuma. Graduation Thesis: Bipedal Robot Control for Reflex Motions, Recovery from Falls, and Soccer Ball Kick, University of Aizu, 2009. Thesis Advisor: R. H. Fujii
[tsuka-08:2009]	Akifumi Hosoya. Graduation Thesis: Reduction of Intermodulation Distortion in Bipolar and MOS Mixers using Parallel Differential Pairs, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara
[tsuka-09:2009]	Mitsuru Suzuki. Graduation Thesis: Noise Canceling Techniques for Low-Noise Amplifiers, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara
[tsuka-10:2009]	Takahiro Tsushima. Graduation Thesis: An Analysis of a Quadrature Mixer and a Proposal of Phase-Error Compensation Designs in High-Frequency Regions, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara
[tsuka-11:2009]	Saeko Yoshinari. Graduation Thesis: An Architectural Study of a Low- Power LMV (LNA, Mixer and VCO) Cell, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara
[tsuka-12:2009]	Hidekazu Usui. Master Thesis: A Current-Mode Sampler with an Embedded Filter Function for Wireless Systems, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara
[tsuka-13:2009]	Tadahiro Yoshida. Master Thesis: A Receiver Using Subsampling and Fourier Transform for Software-Defined Radio Systems, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara
[tsuka-14:2009]	Yuske Sato. Graduation Thesis: An Analysis of Distortion Canceling Methods for Low-Noise Amplifiers, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara
[tsuka-15:2009]	Akio Ogino. Master Thesis: Broadband Design of a Windowed Integration Sampler (WIS) Filter with Linear-phase Characteristics, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara
[tsuka-16:2009]	Kazuya Takahashi. Graduation Thesis: Wideband Design Techniques for Low-Noise Amplifiers, University of Aizu, Feb. 2010. Thesis Advisor: T. Tsukahara

Ph.D, Master and Graduation Theses

[tsuka-17:2009]

T. Tsukahara. Seminar: Design Examples and Perspective of Analog RF CMOS Circuits, June 23 2009 and Jan. 22 2010

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