Lecture Notes of Computer Architecture


 
Lecture 1           :  Course Introduction and Overview of Verilog 
Lecture 2           :  Arithmetic Logic Unit (ALU) and its Verilog Design
Lecture 3           :  Register File and its Design
Lecture 4 (Part 1)  :  Summaries of Verilog Design
Lecture 4 (Part 2)  :  MIPS Instructions
Lecture 5           :  Overview of Single Cycle MIPS
Lecture 6           :  Datapath
Lecture 7           :  A Simple Implementation Scheme
Lecture 8           :  An Overview of Pipeline
Lecture 9           :  A Pipelined Datapath
Lecture 10          :  Pipelined Control and Data Hazards
Lecture 11          :  Data Hazards and Forwarding
Lecture 12          :  Forwarding and Examples
Lecture 13          :  Final Review

 

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