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Fault-tolerant
Interconnect Technologies for SoCs (2D,
3D, Si-Photonics, Hybrid)
Complex signal
processing systems-on-chip contain dozens
of components made of processor cores,
DSPs, memory, accelerators, and I/Os, all
integrated into a single die area of just
a few square millimeters. Such complex
systems need a novel on-chip interconnect
closer to a sophisticated network than
current bus-based solutions. This network
must provide high throughput and low
latency while keeping area and power
consumption low. We research
advanced interconnect technology for
embedded multicore SoCs targeting both FPGA
and ASIC platforms. In
particular, we investigate 3D-TVS
integration, fault tolerance methods,
photonic communication protocols,
low-power mapping techniques, and
low-latency adaptive routing.
Ultra Low-power
Neuromorphic Systems and AI-Accelerators
Neuromorphic
computing uses spiking neuron network
models to solve machine learning problems
in a more power/energy-efficient way when
compared to the conventional artificial
neural networks.We research
adaptive low-power spiking neuromorphic
systems and SoCs empowered with our
earlier developed fault-tolerant
three-dimensional on-chip interconnect
technology. In particular, we
investigate adaptive
configuration methods to enable the
reconfiguration of different network
parameters (spike weights, routing,
hidden layers, topology, etc.),
fault-tolerant and thermal-aware mapping
methods, and on-line learning
algorithms.
Our AI and
neuromorphic AI technology is used in
various real-world applications,
including anthropomorphic
robotics, embedded
medical, and distributed
energy
harvesting
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