Future System‑on‑Chip (SoC) platforms will integrate hundreds of heterogeneous components — processor cores, DSPs, memory blocks, accelerators, and I/O subsystems — within extremely compact silicon footprints. As integration density increases, these systems are evolving beyond traditional bus‑based communication toward sophisticated on‑chip networks and vertically integrated architectures.

Our research addresses the key challenges of this transition by exploring advanced on‑chip interconnects and 3D‑IC technologies, including 3D chiplets, 2.5D/3D packaging, hybrid bonding, and photonic‑electronic interconnects. We investigate scalable and energy‑efficient 3D NoCs, AI accelerators with stacked memory, and reliability‑driven design methodologies to ensure robust operation in deep 3D stacks.

This work tackles critical issues such as fault tolerance, TSV‑based vertical integration, photonic communication, low‑power mapping, adaptive routing, and emerging reliability challenges inherent to next‑generation heterogeneous many‑core systems.

TSV is essential for low-power 3D-ICs, but lifetime reliability is threatened by high operating temperatures that accelerate fault rates. HotCluster is a hotspot-aware self-correction platform for clustering defects in 3D-NoCs. It strategically places redundant TSV groups based on regional heat profiles. By redistributing redundancies, HotCluster reduces hardware overhead by 60% compared to uniform distribution while maintaining system stability under 50% defect rates.

IA-SiG addresses interconnect reliability in 3D-ICs through an online detection and correction method. By analyzing output syndromes, the system localizes and fixes defective TSVs in real-time. Integrating IA-SiG onto 3D-NoCs using a grid-search empirical method allows for temperature-aware redundancy insertion, maintaining the required Mean Time to Failure while minimizing hardware costs.

Photonic links provide massive bandwidth but face scalability issues. We propose a novel Wavelength-Shifting mechanism that combines the benefits of photonic speed with scalable routing. This approach reduces the number of required photonic devices by 60% and achieves latency and power performance an order of magnitude better than electro-assisted architectures, regardless of traffic patterns or communication distance.

Unlike traditional methods that require system interruptions, TSV-OCT (On-Communication Test) detects open and short defects in parallel with active data transactions. Utilizing a statistical detector and isolation-and-check algorithms, it localizes up to 5 times more defects than standard ECC techniques without halting real-time applications.

3D-FTO ensures message delivery in many-core systems even in the presence of transient and permanent faults. The architecture uses a Hybrid-Look-Ahead (HLAFT) routing algorithm and Random-Access-Buffers (RAB) to eliminate deadlocks and relieve congestion. This system achieves a 12.5% reduction in latency and 11.8% throughput enhancement with integrated power management.

• Patent No. 7488989: A three-dimensional system on chip in which a TSV group connects between layers (2024).
  Inventors: Abderazek Ben Abdallah, Khanh N. Dang
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• Patent No. 7239099: TSV Error Tolerant Router Device for 3D Network On Chip (2023).
  Inventors: Abderazek Ben Abdallah, Khanh N. Dang, Masayuki Hisada
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• Patent No. 6846027: Defect tolerance router for network on-chip (2021).
  Inventors: Abderazek Ben Abdallah
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• Patent No. 6747660: Optical network-on-chip system using non-block photo-switches (2020).
  Inventors: Abderazek Ben Abdallah
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• Patent No. 6284177: Error resilience router and control method (2018).
  Inventors: Abderazek Ben Abdallah
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• K. N. Dang, A. B. Ahmed, A. B. Abdallah and X. -T. Tran, "HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 4, pp. 799-812, April 2022
• K. N. Dang, M. C. Meyer, A. B. Ahmed, A. B. Abdallah and X. -T. Tran, "A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip," in IEEE Access, vol. 8, pp. 59571-59589, 2020
• The H. Vu, Yuichi Okuyama, Abderazek Ben Abdallah, “Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithms and Architecture for 3D-NoC of Spiking Neurons,” ACM Journal on Emerging Technologies in Computing Systems (JETC)
• T. H. Vu, O. M. Ikechukwu and A. Ben Abdallah, "Fault-Tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems," in IEEE Access, vol. 7, pp. 90436-90452, 2019
• K. N. Dang, A. B. Ahmed, A. B. Abdallah and X. -T. Tran, "A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems," in IEEE Access, vol. 8, pp. 166642-166657, 2020
• Wang, Jiangkun, Ogbodo Mark Ikechukwu, Khanh N. Dang, and Abderazek Ben Abdallah, "Spike-Event X-ray Image Classification for 3D-NoC-Based Neuromorphic Pneumonia Detection," Electronics 11, no. 24: 4157
• Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, "A Low-overhead Soft-Hard Fault Tolerant Architecture, Design and Management Scheme for Reliable High-performance Many-core 3D-NoC Systems,” Journal of Supercomputing (2017) 73:2705–2729.
• Akram Ben Ahmed, A. Ben Abdallah, "Architecture and Design of High-throughput, Low-latency and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip,” The Journal of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532.
• Akram Ben Ahmed, A. Ben Abdallah, "Architecture and Design of Real-Time Systems for Elderly Health Monitoring," Journal of Embedded Systems, 2017, Vol.9, No.5, pp.484 – 494.
• Akram Ben Ahmed, Abderazek Ben Abdallah, "Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC Systems", Journal of Parallel and Distributed Computing, Volumes 93–94, July 2016, Pages 30-43.
• Akram Ben Ahmed, A. Ben Abdallah,”Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures,” Vournal of Parallel and Distributed Computing, 74/4 (2014), pp. 2229-2240.
• Abderazek Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, “Natural Instruction Level Parallelism-aware Compiler for High-Performance QueueCore Processor Architecture,” The Journal of Supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.
• Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, “Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era,” Proc. IEEE 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013′), July 2013.
• Akram Ben Ahmed, A. Ben Abdallah, “ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications,” IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012.
• A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, “Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoCs,” IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010.
• K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, “Advanced Design Issues for OASIS Network-on-Chip Architecture,” IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.