Advanced On-chip Interconnects

Future System-on-Chip (SoC) will contain hundreds of components made of processor cores, DSPs, memory, accelerators, and I/O all integrated into a single die area of just a few square millimeters. Such complex systems will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions. This network must provide high throughput and low latency while keeping area and power consumption low. Our research solves several design challenges to enable massively parallel many-core systems, specifically investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping, and adaptive routing.

TSV is essential for low-power 3D-ICs, but lifetime reliability is threatened by high operating temperatures that accelerate fault rates. HotCluster is a hotspot-aware self-correction platform for clustering defects in 3D-NoCs. It strategically places redundant TSV groups based on regional heat profiles. By redistributing redundancies, HotCluster reduces hardware overhead by 60% compared to uniform distribution while maintaining system stability under 50% defect rates.

IA-SiG addresses interconnect reliability in 3D-ICs through an online detection and correction method. By analyzing output syndromes, the system localizes and fixes defective TSVs in real-time. Integrating IA-SiG onto 3D-NoCs using a grid-search empirical method allows for temperature-aware redundancy insertion, maintaining the required Mean Time to Failure while minimizing hardware costs.

Photonic links provide massive bandwidth but face scalability issues. We propose a novel Wavelength-Shifting mechanism that combines the benefits of photonic speed with scalable routing. This approach reduces the number of required photonic devices by 60% and achieves latency and power performance an order of magnitude better than electro-assisted architectures, regardless of traffic patterns or communication distance.

Unlike traditional methods that require system interruptions, TSV-OCT (On-Communication Test) detects open and short defects in parallel with active data transactions. Utilizing a statistical detector and isolation-and-check algorithms, it localizes up to 5 times more defects than standard ECC techniques without halting real-time applications.

3D-FTO ensures message delivery in many-core systems even in the presence of transient and permanent faults. The architecture uses a Hybrid-Look-Ahead (HLAFT) routing algorithm and Random-Access-Buffers (RAB) to eliminate deadlocks and relieve congestion. This system achieves a 12.5% reduction in latency and 11.8% throughput enhancement with integrated power management.

• Patent No. 7488989: A three-dimensional system on chip in which a TSV group connects between layers (2024).
  Inventors: Abderazek Ben Abdallah, Khanh N. Dang
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• Patent No. 7239099: TSV Error Tolerant Router Device for 3D Network On Chip (2023).
  Inventors: Abderazek Ben Abdallah, Khanh N. Dang, Masayuki Hisada
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• Patent No. 6846027: Defect tolerance router for network on-chip (2021).
  Inventors: Abderazek Ben Abdallah
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• Patent No. 6747660: Optical network-on-chip system using non-block photo-switches (2020).
  Inventors: Abderazek Ben Abdallah
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• Patent No. 6284177: Error resilience router and control method (2018).
  Inventors: Abderazek Ben Abdallah
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